UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 885

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
(5) Program status word (PSW)
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
PSW
The program status word is a register used to hold the instruction execution result and the current status for an
interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that controls
multiple interrupt servicing are mapped to the PSW.
Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated
instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the
contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt request
is acknowledged, the ISP1 and ISP0 flags are set according to the priority specification level of the acknowledged
interrupt. The PSW contents are also saved into the stack with the PUSH PSW instruction. They are restored from
the stack with the RETI, RETB, and POP PSW instructions.
Reset signal generation sets the PSW register to 06H.
<7>
IE
<6>
Z
RBS1
<5>
<4>
AC
Figure 18-6. Configuration of Program Status Word
RBS0
<3>
ISP1
<2>
ISP0
<1>
CY
0
ISP1
IE
0
0
1
1
0
1
Used when normal instruction is executed
After reset
06H
ISP0
Disabled
Enabled
0
1
0
1
Interrupt request acknowledgment enable/disable
Enables interrupt of level 0
(while interrupt of level 1 or 0 is being serviced).
Enables interrupt of level 0 and 1
(while interrupt of level 2 is being serviced).
Enables interrupt of level 0 to 2
(while interrupt of level 3 is being serviced).
Enables all interrupts
(waits for acknowledgment of an interrupt).
CHAPTER 18 INTERRUPT FUNCTIONS
Priority of interrupt currently being serviced
885