UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 786

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
15.5.9 Address match detection method
set to the slave address register (SVA) matches the slave address sent by the master device, or when an extension code
has been received.
15.5.10 Error detection
(IICA) of the transmitting device, so the IICA data prior to transmission can be compared with the transmitted IICA data to
enable detection of transmission errors. A transmission error is judged as having occurred when the compared data
values do not match.
15.5.11 Extension code
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
In I
Address match can be detected automatically by hardware. An interrupt request (INTIICA) occurs when the address
In I
(1) When the higher 4 bits of the receive address are either “0000” or “1111”, the extension code reception flag (EXC)
(2) The settings below are specified if 11110xx0 is transferred from the master by using a 10-bit address transfer when
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension code,
Remark
2
2
C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address.
C bus mode, the status of the serial data bus (SDA0) during data transmission is captured by the IICA shift register
is set to 1 for extension code reception and an interrupt request (INTIICA) is issued at the falling edge of the eighth
clock. The local address stored in the slave address register (SVA) is not affected.
• Higher four bits of data match: EXC = 1
• Seven bits of data match:
Remark
such processing is performed by software.
If the extension code is received while a slave device is operating, then the slave device is participating in
communication even if its address does not match.
For example, after the extension code is received, if you do not wish to operate the target device as a slave device,
set bit 6 (LREL) of IICA control register 0 (IICCTL0) to 1 to set the standby mode for the next communication
operation.
the SVA register is set to 11110xx0. Note that INTIICA occurs at the falling edge of the eighth clock.
See the I
described above.
Slave Address
EXC:
COI:
0 0 0 0 0 0 0
1 1 1 1 0 x x
1 1 1 1 0 x x
2
C bus specifications issued by NXP Semiconductors for details of extension codes other than those
Bit 5 of IICA status register (IICS)
Bit 4 of IICA status register (IICS)
Table 15-3. Bit Definitions of Major Extension Codes
R/W Bit
COI = 1
0
0
1
General call address
authentication)
read command is issued)
10-bit slave address specification (during address
10-bit slave address specification (after address match, when
CHAPTER 15 SERIAL INTERFACE IICA
Description
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