UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 606

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03),
(7) Serial status register mn (SSRmn)
SSRmn
Symbol
The SSRmn register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the SSRmn register can be set with an 8-bit memory manipulation instruction with SSRmnL.
Reset signal generation clears the SSRmn register to 0000H.
Caution If data is written to the SDRmn register when BFFmn = 1, the transmit/receive data stored in the
The SSRmn register is a register that indicates the communication status and error occurrence status of channel n.
The errors indicated by this register are a framing error, parity error, and overrun error.
Remark m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 3)
F0140H, F0141H (SSR10) to F0146H, F0147H (SSR13),
F0200H, F0201H (SSR20), F0202H, F0203H (SSR21)
<Clear conditions>
• Communication ends.
<Set condition>
• Communication starts.
<Clear conditions>
• Transferring transmit data from the SDRmn register to the shift register ends during transmission.
• Reading receive data from the SDRmn register ends during reception.
• The STmn bit of the STm register is set to 1 (communication is stopped) or the SSmn bit of the SSm register is set
<Set conditions>
• Transmit data is written to the SDRmn register while the TXEmn bit of the SCRmn register is set to 1
• Receive data is stored in the SDRmn register while the RXEmn bit of the SCRmn register is set to 1 (reception or
• A reception error occurs.
• The STmn bit of the STm register is set to 1 (communication is stopped) or the SSmn bit of the SSm register is
TSF
BFF
mn
mn
15
to 1 (communication is enabled).
(transmission or transmission and reception mode in each communication mode).
transmission and reception mode in each communication mode).
0
1
0
1
0
set to 1 (communication is suspended).
register is discarded and an overrun error (OVEmn = 1) is detected.
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L
78K0R/KF3-L
78K0R/KG3-L
78K0R/KG3-L
Communication is stopped or suspended.
Communication is in progress.
Valid data is not stored in the SDRmn register.
Valid data is stored in the SDRmn register.
14
0
Figure 14-11. Format of Serial Status Register mn (SSRmn) (1/2)
13
0
μ
μ
μ
μ
12
0
PD78F1010, 78F1011, 78F1012 :
PD78F1027, 78F1028 :
PD78F1013, 78F1014 :
PD78F1029, 78F1030 :
11
0
Communication status indication flag of channel n
Buffer register status indication flag of channel n
10
0
9
0
8
0
After reset: 0000H
7
0
TSF
mn
6
mn = 00 to 03
mn = 00 to 03, 10 to 13
mn = 00 to 03, 10 to 13, 20, 21
mn = 00 to 03, 10 to 13
mn = 00 to 03, 10 to 13, 20, 21
CHAPTER 14 SERIAL ARRAY UNIT
BFF
mn
5
R
4
0
3
0
FEF
mn
2
PEF
mn
1
OVF
mn
0
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