UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 963

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
Note
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Low consumption
current mode
Normal current mode
Caution 2. A wait is required to change the operation speed mode control register (OSMC) after
The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock. These conditions apply to products other than the
78K0R/KC3-L (40-pin).
Mode
changing the regulator mode control register (RMC). Wait for 3.5 ms by software when
setting to low consumption current mode and 10
described in the procedure shown below.
• When setting to low consumption current mode
• When setting to normal current mode
<1> Select a frequency of 1 MHz for f
<2> Set the RMC register to 5AH (set the regulator to low consumption current mode).
<3> Wait for 3.5 ms.
<4> Set the FLPC and FSEL bits of the OSMC register to 1 and 0, respectively.
<1> Set the RMC register to 00H (set the regulator to normal current mode).
<2> Wait for 10
<3> Change the FLPC and FSEL bits of the OSMC register.
<4> Change the f
1.8 V
2.4 V
Output Voltage
Table 24-1. Regulator Output Voltage Conditions
μ
s.
CLK
In STOP mode (except during OCD mode)
When both the high-speed system clock (f
clock (f
during CPU operation with the subsystem clock (f
When both the high-speed system clock (f
clock (f
during the HALT mode when the CPU operation with the subsystem clock (f
been set
Other than above
frequency.
IH
IH
), and the 20 MHz internal high-speed oscillation clock (f
), and the 20 MHz internal high-speed oscillation clock (f
Note
CLK
.
μ
s when setting to normal current mode, as
Condition
MX
MX
), the high-speed internal oscillation
), the high-speed internal oscillation
CHAPTER 24 REGULATOR
XT
)
Note
IH20
IH20
) are stopped
) are stopped
XT
) has
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