UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 668

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
14.5.5 Slave reception
from another device.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Slave reception is that the 78K0R/Kx3-L receives data from another device in the state of a transfer clock being input
Notes 1. 78K0R/KF3-L, 78K0R/KG3-L only.
Remarks 1. f
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Clock phase
Data direction
3-Wire Serial I/O
2. CSI40 and CSI41 are only mounted in the 78K0R/KF3-L (
3. Because the external serial clock input to the SCK00, SCK01, SCK10, SCK20, SCK40, and SCK41 pins is
4. Use this operation within a range that satisfies the conditions above and the AC characteristics in the
PD78F1029, 78F1030).
sampled internally and used, the fastest transfer rate is the f
electrical specifications (see CHAPTER 30 ELECTRICAL SPECIFICATIONS (78K0R/KC3-L, 78K0R/KD3-L,
78K0R/KE3-L), CHAPTER 31 ELECTRICAL SPECIFICATIONS (78K0R/KF3-L, 78K0R/KG3-L)).
2. m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 2)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L (
78K0R/KF3-L (
78K0R/KG3-L (
78K0R/KG3-L (
MCK
: Operation clock frequency of target channel
Channel 0 of
SAU0
SCK00, SI00
INTCSI00
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Overrun error detection flag (OVFmn) only
7 or 8 bits
Max. f
Selectable by the DAPmn bit of the SCRmn register
• DAPmn = 0: Data input starts from the start of the operation of the serial clock.
• DAPmn = 1: Data input starts half a clock before the start of the serial clock operation.
Selectable by the CKPmn bit of the SCRmn register
• CKPmn = 0: Forward
• CKPmn = 1: Reverse
MSB or LSB first
CSI00
μ
μ
μ
μ
MCK
PD78F1010, 78F1011, 78F1012):
PD78F1027, 78F1028):
PD78F1013, 78F1014):
PD78F1029, 78F1030):
/6 [Hz]
Notes 3, 4
Channel 1 of
SAU0
SCK01, SI01
INTCSI01
CSI01
Channel 2 of
SAU0
SCK10, SI10
INTCSI10
CSI10
mn = 00 to 02
mn = 00 to 02, 10
mn = 00 to 02, 10, 20, 21
mn = 00 to 02, 10
mn = 00 to 02, 10, 20, 21
MCK
μ
Channel 0 of
SAU1
SCK20, SI20
INTCSI20
CSI20
PD78F1027, 78F1028) and 78K0R/KG3-L (
/6 [Hz] .
CHAPTER 14 SERIAL ARRAY UNIT
Note 1
Channel 0 of
SAU2
SCK40, SI40
INTCSI40
CSI40
Note 2
Channel 1 of
SAU2
SCK41, SI41
INTCSI41
CSI41
Note 2
668
μ