UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 710

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(3) Permissible baud rate range for reception
The permissible baud rate range for reception during UART (UART0 to UART4) communication can be calculated
by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud
rate range at the reception side.
Remark m: Unit number (m = 0 to 2), n: Channel number (n = 1, 3)
As shown in Figure 14-89, the timing of latching receive data is determined by the division ratio set by bits 15 to 9
of serial data register mn (SDRmn) after the start bit is detected. If the last data (stop bit) is received before this
latch timing, the data can be correctly received.
(Maximum receivable baud rate) =
(Minimum receivable baud rate) =
Brate: Calculated baud rate value at the reception side (See 14.6.3 (1) Baud rate calculation expression.)
k:
Nfr:
Permissible maximum
Permissible minimum
Data frame length
Figure 14-89. Permissible Baud Rate Range for Reception (1 Data Frame Length = 11 Bits)
data frame length
data frame length
SDRmn[15:9] + 1
1 data frame length [bits]
= (Start bit) + (Data length) + (Parity bit) + (Stop bit)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L(
78K0R/KF3-L(
78K0R/KG3-L(
78K0R/KG3-L(
of SAU
μ
μ
μ
μ
PD78F1010, 78F1011, 78F1012):
PD78F1027, 78F1028):
PD78F1013, 78F1014):
PD78F1029, 78F1030):
timing
Latch
Start
Start
bit
Start
bit
bit
2 × k × Nfr − k + 2
2 × k × Nfr − k − 2
Bit 0
2 × k × (Nfr − 1)
Bit 0
FL
Bit 0
2 × k × Nfr
Bit 1
Bit 1
Bit 1
1 data frame (11 × FL)
(11 × FL) min.
(11 × FL) max.
× Brate
× Brate
mn = 01, 03
mn = 01, 03, 11, 13
mn = 01, 03, 11, 13, 21
mn = 01, 03, 11, 13
mn = 01, 03, 11, 13, 21
Bit 7
CHAPTER 14 SERIAL ARRAY UNIT
Bit 7
Bit 7
Parity
bit
Parity
bit
Parity
bit
Stop
bit
Stop
bit
Stop
bit
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