UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 657

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Figure 14-51. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode)
Caution
Remark
<1> Select the buffer empty interrupt.
<1> to <8> in the figure correspond to <1> to <8> in Figure 14-50
Transmission/Reception (in Continuous Transmission/Reception Mode).
Writing 1 to the MDmn0 bit
After setting the SAUmEN bit of peripheral enable register 0/1 (PER0/PER1) to 1, be sure to set
serial clock select register m (SPSm) after 4 or more f
<3>
<6>
Yes
No
SMRmn, SCRmn:
SDRmn[15:9]:
SOm, SOEm:
<2>
<4>
<8>
<5>
<7>
Clearing 0 to the MDmn0 bit
Clearing the SAUmEN bit of the
Setting the SAUmEN bit of the
Reading receive data from
Reading receive data from
Setting operation clock by
Writing 1 to the SSmn bit
Writing 1 to the STmn bit
Starting CSI communication
Writing transmit data to
End of communication
Communication continued?
PER0/PER1 register to 1
PER0/PER1 register to 0
SIOp (=SDRmn[7:0])
SIOp (=SDRmn[7:0])
SIOp (=SDRmn[7:0])
the SPSm register
Communication data
Port manipulation
Buffer empty interrupt
Transfer end interrupt
Setting communication
Setting transfer rate
Setting output and SCKp output
No
TSFmn = 1?
Yes
Yes
generated?
generated?
exists?
Yes
No
No
No
Yes
CLK
CHAPTER 14 SERIAL ARRAY UNIT
clocks have elapsed.
Specify the initial settings while the
SEmn bit of serial channel enable status
register m (SEm) is 0 (operation is
stopped).
Timing Chart of Master
657