UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 745

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
Notes 1. Serial channel enable status register 0 (SE0) is a read-only status register which is set using serial channel start
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Remark X: Don’t care
Note 1
SE
02
0
1
0
1
0
Table 14-7. Relationship Between Register Settings and Pins (Channel 2: CSI10, UART1 Transmission, IIC10)
MD
022
0
0
1
0
0
1
2. When channel 3 is set to UART1 reception, this pin becomes an RxD1 function pin (refer to Table 14-8). In this
3. This pin can be set as a port function pin.
4. This is 0 or 1, depending on the communication operation. For details, refer to 14.3 (12) Serial output register
5. When using UART1 transmission and reception in a pair, set channel 3 to UART1 reception (refer to Table 14-8).
6. Set the CKO02 bit to 1 before a start condition is generated. Clear the SO02 bit from 1 to 0 when the start
7. Set the CKO02 bit to 1 before a stop condition is generated. Clear the SO02 bit from 0 to 1 when the stop
021
MD
case, operation stop mode or UART1 transmission must be selected for channel 2.
condition is generated.
condition is generated.
register 0 (SS0) and serial channel stop register 0 (ST0).
m (SOm).
0
1
0
0
1
0
SOE
02
0
0
1
1
0
1
1
1
0
1
1
1
0
Note 4
Note 7
0/1
Note 4
0/1
Note 4
0/1
Note 4
0/1
Note 4
0/1
Note 4
0/1
Note 6
0/1
Note 4
0/1
Note 4
0/1
0/1
SO
02
1
1
1
CKO
Note 4
Note 4
Note 4
Note 6
Note 4
Note 4
Note 4
Note 7
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
02
1
1
1
1
1
TXE
02
0
0
1
1
0
1
1
1
0
1
0
1
1
0
0
1
0
RXE
02
0
1
0
1
1
0
1
0
0
0
1
0
0
1
0
0
1
PM3
Note 3
Note 3
×
×
0
0
0
0
0
2
1
1
1
0
0
0
P32 PM
Note 3
Note 3
×
×
×
×
×
1
1
1
1
1
1
1
1
Note 2
Note 3
Note 3
Note 3
Note 3
31
0
0
×
×
×
×
1
1
1
1
0
0
0
P31
Note 3
Note 3
Note 3
Note 3
Note 2
×
×
×
×
×
×
×
×
1
1
1
1
1
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
PM
30
×
×
×
0
×
×
×
×
×
0
0
0
0
P30
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
×
×
×
1
1
×
1
1
1
×
×
×
×
Operation stop
start condition
stop condition
Master CSI10
Master CSI10
transmission
transmission
transmission
IIC10 address
transmission
Slave CSI10
Slave CSI10
Master CSI10
transmission
transmission
transmission
Slave CSI10
IIC10 data
IIC10 data
Operation
reception
reception
reception
/reception
/reception
UART1
mode
mode
IIC10
IIC10
Note5
field
CHAPTER 14 SERIAL ARRAY UNIT
INTP2/P32
INTP2/P32
INTP2/P32
(output)
(output)
(output)
SCK10/
SCL10/
SCK10
SCK10
SCK10
SCK10
SCK10
SCK10
SCL10
SCL10
SCL10
SCL10
SCL10
(input)
(input)
(input)
Pin Function
RxD1/INTP1/
RxD1/INTP1/
RxD1/INTP1/
SI10/SDA10/
INTP1/P31
INTP1/P31
INTP1/P31
INTP1/P31
P31
SDA10
SDA10
SDA10
SDA10
SDA10
SI10
SI10
SI10
SI10
P31
P31
Note 2
TxD1/P30
SO10/
SO10
SO10
SO10
SO10
TxD1
P30
P30
P30
P30
P30
P30
P30
P30
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