UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 937

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
22.4 Cautions for Power-on-Clear Circuit
(V
of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
POR
Note 1
In a system where the supply voltage (V
<Action>
• If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
Notes 1.
Remark m = 0, 1, n = 0 to 7
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software
counter that uses a timer, and then initialize the ports.
, V
PDR
2.
), the system may be repeatedly reset and released from the reset status. In this case, the time from release
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
If reset is generated again during this period, initialization processing <2> is not started.
A flowchart is shown on the next page.
No
Figure 22-3. Example of Software Processing After Reset Release (1/2)
Setting timer array unit
(to measure 50 ms)
50 ms has passed?
processing <1>
processing <2>
(TMIFmn = 1?)
Clearing WDT
Initialization
Initialization
Reset
Yes
Power-on-clear
DD
) fluctuates for a certain period in the vicinity of the POC detection voltage
;
; f
; Initial setting for port.
Check the reset source, etc.
Setting of division ratio of system clock,
such as setting of timer or A/D converter.
CLK
Source: f
Timer starts (TSmn = 1).
mn = 00 to 07, 10 to 13
= Internal high-speed oscillation clock (8.16 MHz (MAX.)/2) (default)
where comparison value = 796: ≅ 50 ms
MCK
CHAPTER 22 POWER-ON-CLEAR CIRCUIT
(8.16 MHz (MAX.)/2)/2
Note 2
8
,
937