UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 751

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note 1
SE
10
0
1
0
1
0
78K0R/Kx3-L
Notes 1. Serial channel enable register 1 (SE1) is a read-only status register which is set using serial channel statrt
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Remark X: Don’t care
MD
102
0
0
1
0
0
1
2. When channel 1 of unit 1 is set to UART2 reception, this pin becomes an RxD2 function pin (refer to Table 14-
3. This pin can be set as a port function pin.
4. This is 0 or 1, depending on the communication operation. For details, refer to 14.3 (12) Serial output register
5. When using UART2 transmission and reception in a pair, set channel 1 of unit 1 to UART2 reception (refer to
6. Set the CKO10 bit to 1 before a start condition is generated. Clear the SO10 bit from 1 to 0 when the start
7. Set the CKO10 bit to 1 before a stop condition is generated. Clear the SO10 bit from 0 to 1 when the stop
MD
101
0
1
0
0
1
0
14). In this case, operation stop mode or UART2 transmission must be selected for channel 0 of unit 1.
m (SOm).
Table 14-14).
condition is generated.
condition is generated.
register 1 (SS1) and serial channel stop register 1 (ST1).
SOE
10
0
0
1
1
0
1
1
1
0
1
1
1
0
Note 4
Note 4
Note 4
Note 4
Note 4
Note 6
Note 4
Note 4
Note 4
Note 7
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
SO
10
1
1
1
Note 4
Note 4
Note 4
Note 6
Note 4
Note 4
Note 4
Note 7
CKO
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
10
1
1
1
1
1
TXE
10
Table 14-13. Relationship between register settings and pins
0
0
1
1
0
1
1
1
0
1
0
1
1
0
0
1
0
(Channel 0 of unit 1: CSI20, UART2 transmission, IIC20)
RXE
10
0
1
0
1
1
0
1
0
0
0
1
0
0
1
0
0
1
Note 3
Note 3
142
PM
×
1
1
1
0
0
0
×
0
0
0
0
0
P142 PM
Note 3
Note 3
×
×
×
×
1
1
1
×
1
1
1
1
1
Note 2
Note 3
Note 3
Note 3
Note 3
143
×
1
×
1
1
×
1
×
0
0
0
0
0
P143
Note 3
Note 3
Note 3
Note 3
Note 2
×
×
×
×
×
×
×
×
1
1
1
1
1
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
144
PM
×
×
0
0
×
0
0
0
×
×
×
×
×
P144
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
×
×
1
1
×
1
1
1
×
×
×
×
×
transmission/reception
transmission/reception
IIC20 address field
Operation mode
transmission
Operation stop
start condition
Master CSI20
Master CSI20
stop condition
Slave CSI20
Slave CSI20
transmission
transmission
transmission
Master CSI20
transmission
Slave CSI20
IIC20 data
IIC20 data
reception
reception
reception
UART2
mode
IIC20
IIC20
CHAPTER 14 SERIAL ARRAY UNIT
Note 5
SCL20/P142
(output)
(output)
(output)
SCK20/
SCK20
SCK20
SCK20
SCK20
SCK20
SCK20
SCL20
SCL20
SCL20
SCL20
SCL20
(input)
(input)
(input)
P142
P142
Pin Function
SI20/SDA20/
P143/RxD2
P143/RxD2
RxD2/P143
SDA20
SDA20
SDA20
SDA20
SDA20
P143
P143
P143
P143
Note 2
SI20
SI20
SI20
SI20
TxD2/P144
SO20/
SO20
SO20
SO20
SO20
TxD2
P144
P144
P144
P144
P144
P144
P144
P144
751