UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 836

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(communication status)
(communication status)
(2) Address ~ data ~ data
(8 or 9 clock wait)
(8 or 9 clock wait)
(wait cancellation)
(wait cancellation)
(transmit/receive)
(transmit/receive)
(ACK detection)
(ACK detection)
(ST detection)
(SP detection)
Master side
(ACK control)
(ACK control)
Slave side
(ST trigger)
(SP trigger)
SCL0 (bus)
SDA0 (bus)
(clock line)
Notes 1. To cancel master wait, write “FFH” to IICA or set the WREL bit.
Bus line
(data line)
(interrupt)
(interrupt)
INTIICA
INTIICA
WTIM
WTIM
MSTS
WREL
MSTS
WREL
ACKD
ACKE
ACKD
ACKE
TRC
SPD
TRC
IICA
STT
SPT
IICA
STD
2. Write data to IICA, not setting the WREL bit, in order to cancel a wait state during slave transmission.
(When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3)
H
H
L
L
L
<3>
L
H
H
L
L
H
R
ACK
<6>
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
<5>
Figure 15-33. Example of Slave to Master Communication
<4>
Note 2
<7>
D
1
Note 1
7
D
1
6
D
1
5
D
1
4
D
1
3
D
1
2
CHAPTER 15 SERIAL INTERFACE IICA
D
1
1
<8>
D
1
0
<10>
<9>
ACK
Note 1
<12>
<11>
Note 2
D
2
7
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