UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 601

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03),
SCRmn
Symbol
Note 0 is always added regardless of the data contents.
Caution Be sure to clear bits 3, 6, and 11 to “0”. Be sure to set bit 2 to “1”.
Remark
F0158H, F0159H (SCR10) to F015EH, F015FH (SCR13),
F020CH, F020DH (SCR20), F020EH, F020FH (SCR21)
Figure 14-8. Format of Serial Communication Operation Setting Register mn (SCRmn) (3/4)
Be sure to set PTCmn1, PTCmn0 = 0, 0 in the CSI mode and simplified I
Be sure to clear DIRmn = 0 in the simplified I
When the transfer end interrupt is selected, the interrupt is generated when all stop bits have been completely
transferred.
Set 1 bit (SLCmn1, SLCmn0 = 0, 1) during UART reception and in the simplified I
Set no stop bit (SLCmn1, SLCmn0 = 0, 0) in the CSI mode.
PTC
mn1
SLC
mn1
TXE
DIR
mn
mn
15
0
0
1
1
0
1
0
0
1
1
m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 3)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L
78K0R/KF3-L
78K0R/KG3-L
78K0R/KG3-L
Inputs/outputs data with MSB first.
Inputs/outputs data with LSB first.
PTC
mn0
SLC
mn0
RXE
mn
14
0
1
0
1
0
1
0
1
Does not output the parity bit.
Outputs 0 parity
Outputs even parity.
Outputs odd parity.
No stop bit
Stop bit length = 1 bit
Stop bit length = 2 bits
Setting prohibited
DAP
mn
13
μ
μ
CKP
μ
μ
mn
12
PD78F1010, 78F1011, 78F1012 :
PD78F1027, 78F1028 :
PD78F1013, 78F1014 :
PD78F1029, 78F1030 :
11
Note
Selection of data transfer sequence in CSI and UART modes
0
Transmission
.
EOC
mn
10
PTC
mn1
2
C mode.
9
Setting of parity bit in UART mode
Setting of stop bit in UART mode
PTC
mn0
8
After reset: 0087H
DIR
mn
7
Receives without parity
No parity judgment
Judged as even parity.
Judges as odd parity.
6
0
mn = 00 to 03
mn = 00 to 03, 10 to 13
mn = 00 to 03, 10 to 13, 20, 21
mn = 00 to 03, 10 to 13
mn = 00 to 03, 10 to 13, 20, 21
2
CHAPTER 14 SERIAL ARRAY UNIT
C mode.
SLC
mn1
5
R/W
2
SLC
mn0
C mode.
4
Reception
3
0
DLS
mn2
2
DLS
mn1
1
DLS
mn0
0
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