XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet - Page 103

• Manufacturer Part Number: XC56309VL100A
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VL100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2 Host Port Signals
The host port signals are discussed in Chapter 2, Signals/Connections. Each host port signal can
be programmed as a host port signal or as a GPIO signal, PB[0–15]. See Table 6-1 through
Table 6-3.
The HI08 port can operate in multiplexed or non-multiplexed mode. In multiplexed mode
(HPCR[11]:HMUX = 1), the lower eight address signals multiplex with the eight data lines. In
non-multiplexed mode (HPCR[11]:HMUX = 0), the HI08 requires a chip select signal and three
address lines to select one of the eight registers accessible to the host. Eight lines are used for
data. The HI08 port can also be programmed to use a single or dual read/write data strobe and
single or double host request.
Software and hardware resets clear all DSP-side control registers and configure the HI08 as
GPIO. To select GPIO functions, clear HPCR bits 6 through 1; to select other HI08 functions, set
those same bits. If the HI08 is in GPIO mode, the HDDR configures each corresponding signal in
the HDR as an input signal if the HDDR bit is cleared or as an output signal if the HDDR bit is
set. For details, see Section 6.6.3, Host Data Direction Register (HDDR), on page 6-14 and
Section 6.6.4, Host Data Register (HDR), on page 6-15.
Freescale Semiconductor
HI08 Port Signal
HI08 Port Signal
HI08 Port Signal
HRW/HRD
HDS/HWR
HREQ/
HCS/HA10
HACK/
HRRQ
HTRQ
HAD[0–7]
HAS/HA0
HA8/HA1
HA9/HA2
Table 6-1. HI08 Signal Definitions for Operational Modes
Multiplexed Address/Data Bus Mode
Single Host Request Mode
Single Strobe Mode
HREQ/HREQ
HACK/HACK
HDS/HDS
Table 6-3. HI08 Host Request Signals
Table 6-2. HI08 Data Strobe Signals
HRW
HAD[0–7]
HAS/HAS
HA10
HA8
HA9
DSP56309 User’s Manual, Rev. 1
Double Host Request Mode
Dual Strobe Mode
HRRQ/HRRQ
HTRQ/HTRQ
Non-multiplexed Bus Mode
HWR/HWR
HRD/HRD
HCS/HCS
H[0–7]
HA0
HA1
HA2
GPIO Mode
GPIO Mode
Host Port Signals
PB11
PB12
PB14
PB15
GPIO Mode
PB[0–7]
PB10
PB13
PB8
PB9
6-3