XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet - Page 194

IC DSP 24BIT 100MHZ 196-MAPBGA

XC56309VL100A

Manufacturer Part Number
XC56309VL100A
Description
IC DSP 24BIT 100MHZ 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
DSP563xxr
Type
Fixed Pointr
Datasheets

Specifications of XC56309VL100A

Interface
Host Interface, SSI, SCI
Clock Rate
100MHz
Non-volatile Memory
ROM (576 B)
On-chip Ram
24kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
196-MAPBGA
Device Core Size
24b
Format
Fixed Point
Clock Freq (max)
100MHz
Mips
100
Device Input Clock Speed
100MHz
Ram Size
102KB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC56309VL100A
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
XC56309VL100AR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Triple Timer Module
9.1.2 Individual Timer Block Diagram
Figure 9-2 shows the structure of an individual timer block. The DSP56309 treats each timer as a
memory-mapped peripheral with four registers occupying four 24-bit words in the X data
memory space. The three timers are identical in structure and function. Either standard polled or
interrupt programming techniques can be used to service the timers. A single, generic timer is
discussed in this chapter. Each timer includes the following:
The timer mode is controlled by the TC[3–0] bits which are TCSR[7–4]. For a listing of the timer
modes and descriptions of their operations, see Section 9.3, Operating Modes, on page 9-5.
9-2
24-bit counter
24-bit read/write Timer Control and Status Register (TCSR)
24-bit read-only Timer Count Register (TCR)
24-bit write-only Timer Load Register (TLR)
24-bit read/write Timer Compare Register (TCPR)
Logic for clock selection and interrupt/DMA trigger generation.
GDB
Timer Prescaler
Load Register
24
CLK/2
TPLR
24-bit Counter
Figure 9-1. Triple Timer Module Block Diagram
TIO0 TIO1 TIO2
Timer Prescaler
Count Register
24
DSP56309 User’s Manual, Rev. 1
TPCR
24
Timer 0
Timer 1
Timer 2
24
Freescale Semiconductor

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