XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet - Page 39

• Manufacturer Part Number: XC56309VL100A
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VL100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
SCK0
PC3
SRD0
PC4
STD0
PC5
Notes: 1.
Signal
Name
2.
Input/Output
Input or Output
Input
Input or Output
Output
Input or Output
Table 2-12. Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued)
In the Stop state, the signal maintains the last state as follows:
•
•
The Wait processing state does not affect the signal state.
Type
If the last state is input, the signal is an ignored input.
If the last state is output, these lines are tri-stated.
Ignored input
Ignored input
Ignored input
State During
Reset
1, 2
DSP56309 User’s Manual, Rev. 1
Serial Clock
Provides the serial bit rate clock for the ESSI interface for both the transmitter
and receiver in Synchronous modes, or the transmitter only in Asynchronous
modes.
Although an external serial clock can be independent of and asynchronous to
the DSP system clock, it must exceed the minimum clock cycle time of 6 T
(that is, the system clock frequency must be at least three times the external
ESSI clock frequency). The ESSI needs at least three DSP phases inside
each half of the serial clock.
Port C 3
The default configuration following reset is GPIO. For PC3, signal direction is
controlled through PRRC. This signal is configured as SCK0 or PC3 through
PCRC. This input is 5 V tolerant.
Serial Receive Data
Receives serial data and transfers the data to the ESSI receive shift register.
SRD0 is an input when data is being received.
Port C 4
The default configuration following reset is GPIO. For PC4, signal direction is
controlled through PRRC. This signal is configured as SRD0 or PC4 through
PCRC. This input is 5 V tolerant.
Serial Transmit Data
Transmits data from the serial transmit shift register. STD0 is an output when
data is being transmitted.
Port C 5
The default configuration following reset is GPIO. For PC5, signal direction is
controlled through PRRC. This signal is configured as STD0 or PC5 through
PCRC. This input is 5 V tolerant.
Enhanced Synchronous Serial Interface 0 (ESSI0)
Signal Description
2-15