XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet - Page 138

• Manufacturer Part Number: XC56309VL100A
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VL100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Synchronous Serial Interface (ESSI)
7.3 Operation
This section discusses ESSI basics: reset state, initialization, and exceptions.
7.3.1 ESSI After Reset
A hardware
direction control register, thus configuring all the ESSI signals as GPIO. The ESSI is in the reset
state while all ESSI signals are programmed as GPIO; it is active only if at least one of the ESSI
I/O signals is programmed as an ESSI signal.
7.3.2 Initialization
To initialize the ESSI, do the following:
When the PC[5–0] bits in the GPIO Port Control Register (PCR) are cleared during program
execution, the ESSI stops serial activity and enters the individual reset state. All status bits of the
interface are set to their reset state. The contents of CRA and CRB are not affected. The ESSI
individual reset allows a program to reset each interface separately from the other internal
peripherals. During ESSI individual reset, internal DMA accesses to the data registers of the
ESSI are not valid, and data read there are undefined. To ensure proper operation of the ESSI, use
an ESSI individual reset when you change the ESSI control registers (except for bits TEIE, REIE,
TLIE, RLIE, TIE, RIE, TE2, TE1, TE0, and RE).
Here is an example of how to initialize the ESSI.
7-6
1.
2.
3.
4.
5.
1.
2.
3.
4.
5.
Send a reset: hardware
or stop instruction reset.
Program the ESSI control and time slot registers.
Write data to all the enabled transmitters.
Configure at least one signal as ESSI signal.
If an external frame sync is used, from the moment the ESSI is activated, at least five (5)
serial clocks are needed before the first external frame sync is supplied. Otherwise,
improper operation may result.
Put the ESSI in its individual reset state by clearing the PCR bits.
Configure the control registers (CRA, CRB) to set the operating mode. Disable the
transmitters and receiver by clearing the TE[2–0] and RE bits. Set the interrupt enable
bits for the operating mode chosen.
Enable the ESSI by setting the PCR bits to activate the input/output signals to be used.
Write initial data to the transmitters that are in use during operation. This step is needed
even if DMA services the transmitters.
Enable the transmitters and receiver to be used.
RESET
signal or software reset instruction clears the port control register and the port
RESET
DSP56309 User’s Manual, Rev. 1
signal, software reset instruction, ESSI individual reset,
Freescale Semiconductor