XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet - Page 33

• Manufacturer Part Number: XC56309VL100A
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VL100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.7 Host Interface (HI08)
The HI08 provides a fast, parallel data-to-8-bit port that can directly connect to the host bus. The
HI08 supports a variety of standard buses and can directly connect to a number of
industry-standard microcomputers, microprocessors, DSPs, and DMA hardware.
Freescale Semiconductor
Signal Name
MODC/IRQC
MODD/IRQD
Input
Input
Type
Input
Input
During
Reset
Table 2-9. Interrupt and Mode Control (Continued)
State
Mode Select C/External Interrupt Request C
Selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. MODA, MODB, MODC, and MODD select one of
sixteen initial chip operating modes, latched into OMR when the RESET signal is
deasserted.
Internally synchronized to CLKOUT. If IRQC is asserted synchronous to CLKOUT,
multiple processors can be re-synchronized using the WAIT instruction and asserting
IRQC to exit the Wait state.
MODC/IRQC can tolerate 5 V.
Mode Select D/External Interrupt Request D
Selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. MODA, MODB, MODC, and MODD select one of
sixteen initial chip operating modes, latched into OMR when the RESET signal is
deasserted.
Internally synchronized to CLKOUT. If IRQD is asserted synchronous to CLKOUT,
multiple processors can be re-synchronized using the WAIT instruction and asserting
IRQD to exit the Wait state.
MODD/IRQD can tolerate 5 V.
DSP56309 User’s Manual, Rev. 1
Signal Description
Host Interface (HI08)
2-9