XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet - Page 196

• Manufacturer Part Number: XC56309VL100A
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VL100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Triple Timer Module
9.2.3 Timer Exceptions
Each timer can generate two different exceptions:
To configure a timer exception, perform the following steps. The example at the right of each
step shows the register settings for configuring a Timer 0 compare interrupt. The order of the
steps is optional except that the timer should not be enabled (step 2e) until all other exception
configuration is complete:
9-4
3.
4.
1.
2.
Timer Overflow (highest priority) — Occurs when the timer counter reaches the overflow
value. This exception sets the TOF bit. TOF is cleared when a value of one is written to it
or when the timer overflow exception is serviced.
Timer Compare (lowest priority) — Occurs when the timer counter reaches the value
given in the Timer Compare Register (TCPR) for all modes except measurement modes.
In measurement modes 4–6, a compare exception occurs when the appropriate transition
occurs on the
value of one is written to it or when the timer compare interrupt is serviced.
Configure other registers: Timer Prescaler Load Register (TPLR), Timer Load Register
(TLR), and Timer Compare Register (TCPR) as needed for the application.
Enable the timer by setting the TCSR[TE] bit.
Configure the interrupt service routine (ISR):
a.
b.
c.
Configure the interrupt trigger:
a.
b.
c.
d.
e.
Load vector base address register
Define I_VEC to be equal to the VBA value (if that is nonzero). If it is defined,
I_VEC must be defined for the assembler before the interrupt equate file is
included.
Load the exception vector table entry: two-word fast interrupt, or jump/branch to
subroutine (long interrupt).
Enable and prioritize overall peripheral interrupt functionality.
Enable a specific peripheral interrupt.
Unmask interrupts at the global level.
Configure a peripheral interrupt-generating function.
Enable peripheral and associated signals.
TIO
signal. The Compare exception sets the TCF bit. TCF is cleared when a
DSP56309 User’s Manual, Rev. 1
VBA (b23–8)
p:TIM0C
IPRP (TOL[1–0])
TCSR0 (TCIE)
SR (I[1–0])
TCSR0 (TC[7–4])
TCSR0 (TE)
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