XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet - Page 49

• Manufacturer Part Number: XC56309VL100A
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VL100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.4 Dynamic Memory Configuration Switching
Do not change the OMR[MS] bit when the SR[CE] bit is set. The Instruction Cache occupies the
top 1 K of what is otherwise Program RAM, and to switch memory into or out of Program RAM
when the cache is enabled can cause conflicts. To change the MS bit when CE is set:
Because an interrupt could cause the DSP to fetch instructions out of sequence and might violate
the switch condition, special care should be taken in relation to the interrupt vector routines.
3.5 Sixteen-Bit Compatibility Mode Configuration
The sixteen-bit compatibility (SC) mode allows the DSP56309 to use DSP56000 object code
without change. The SC bit (Bit 13 in the SR) is used to switch from the default 24-bit mode to
this special 16-bit mode. SC is cleared by reset. You must set this bit to select the SC mode. The
address ranges described in the previous sections apply in the SC mode with regard to the
reallocation of X and Y data memory to program memory in MS mode, but the maximum
addressing ranges are limited to $FFFF, and all data and program code are 16 bits wide.
Freescale Semiconductor
1.
2.
3.
Clear CE.
Change MS.
Set CE.
To ensure that dynamic switching is trouble-free, do not allow any
accesses (including instruction fetches) to or from the affected address
ranges in program and data memories during the switch cycle.
Pay special attention when executing a memory switch routine using the
OnCE port. Running the switch routine in trace mode, for example, can
cause the switch to complete after the MS/MSW bits change while the DSP
is in Debug mode. As a result, subsequent instructions may be fetched
according to the new memory configuration (after the switch) and thus
may execute improperly.
DSP56309 User’s Manual, Rev. 1
CAUTION
CAUTION
Dynamic Memory Configuration Switching
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