XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet - Page 135

• Manufacturer Part Number: XC56309VL100A
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VL100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

transmitted, the
programmed as a GPIO signal (
7.2.2 Serial Receive Data Signal (SRD)
SRD
programmed as a GPIO signal (
7.2.3 Serial Clock (SCK)
SCK
a clock input or output used by all the enabled transmitters and receivers in Synchronous modes
or by all the enabled transmitters in Asynchronous modes. See Table 7-1 for details.
programmed as a GPIO signal (
Note:
7.2.4 Serial Control Signal (SC0)
ESSI0: SC00; ESSI1: SC10
To determine the function of the
according to Table 7-2. In Asynchronous mode, this signal is used for the receive clock I/O. In
Synchronous mode, this signal is the transmitter data out signal for transmit shift register TX1 or
for serial flag I/O. A typical application of serial flag I/O would be multiple device selection for
addressing in codec systems.
If
the Serial Control Direction 0 (SCD0) bit in ESSI Control Register B (CRB). When configured as
an output,
Freescale Semiconductor
SC0
SYN
0
0
0
0
1
1
is a bidirectional signal providing the serial bit rate clock for the ESSI interface. The signal is
receives serial data and transfers the data to the receive shift register.
is configured as a serial flag signal or receive clock signal, its direction is determined by
Although an external serial clock can be independent of and asynchronous to the DSP
system clock, the external ESSI clock frequency must not exceed F
ESSI phase must exceed the minimum of 1.5
ESSI clock frequency must not exceed F
SC0
SCKD
0
0
1
1
0
1
functions as the serial Output Flag 0 (OF0) or as a receive shift register clock
STD
signal does not assume a high-impedance state. The
SCD0
0/1
0/1
0
1
0
1
P5
P4
P3
Table 7-1. ESSI Clock Sources
RX Clock Source
SC0
) when the ESSI
) when the
) when not used as the ESSI clock.
DSP56309 User’s Manual, Rev. 1
EXT, SCK
EXT, SC0
EXT, SC0
signal, select either Synchronous or Asynchronous mode,
INT
INT
INT
Asynchronous
Synchronous
SRD
function is not in use.
RX Clock
STD
core
SCK
SC0
SC0
Out
—
—
—
/4.
function is not in use.
CLKOUT
TX Clock Source
cycles. The internally sourced
EXT, SCK
EXT, SCK
EXT, SCK
INT
INT
INT
ESSI Data and Control Signals
STD
SRD
signal can be
core
can be
/3, and each
TX Clock Out
SCK
SCK
SCK
SCK
—
—
—
can be
7-3