XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet - Page 121

• Manufacturer Part Number: XC56309VL100A
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VL100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

techniques. The HI08 appears to the host processor as a memory-mapped peripheral occupying
eight bytes in the host processor address space. (See Table 6-14.)
The eight HI08 registers include the following:
To transfer data between itself and the HI08, the host processor bus performs the following steps:
Host processors can use standard host processor instructions (for example, byte move) and
addressing modes to communicate with the HI08 registers. The HI08 registers are aligned so that
8-bit host processors can use 8-, 16-, or 24-bit load and store instructions for data transfers. The
HREQ/HTRQ and HACK/HRRQ handshake flags are provided for polled or interrupt-driven
data transfers with the host processor. Because of the speed of the DSP56309 interrupt response,
most host microprocessors can load or store data at their maximum programmed I/O instruction
rate without testing the handshake flags for each transfer. If full handshake is not needed, the host
processor can treat the DSP56309 as a fast device, and data can be transferred between the host
processor and the DSP56309 at the fastest data rate of the host processor.
One of the most innovative features of the host interface is the host command feature. With this
feature, the host processor can issue vectored interrupt requests to the DSP56309. The host can
select any of 128 DSP interrupt routines for execution by writing a vector address register in the
HI08. This flexibility allows the host processor to execute up to 128 pre-programmed functions
inside the DSP56309. For example, the DSP56309 host interrupts allow the host processor to
read or write DSP registers (X, Y, or program memory locations), force interrupt handlers (for
example, ESSI, SCI,
operations.
Note:
Freescale Semiconductor
1.
2.
3.
A control register (ICR), on page 6-22
A status register (ISR), on page 6-24
Three data registers (RXH/TXH, RXM/TXM, and RXL/TXL), on page 6-26
Two vector registers (CVR and IVR), on page 6-24 and page 6-26
Asserts the HI08 address and strobes to select the register to be read or written. (Chip
select in non-multiplexed mode, the address strobe in multiplexed mode.)
Selects the direction of the data transfer. If it is writing, the host processor places the
data on the bus. Otherwise, the HI08 places the data on the bus.
Strobes the data transfer.
When the DSP enters Stop mode, the HI08 signals are electrically disconnected
internally, thus disabling the HI08 until the core leaves stop mode. While the HI08
configuration remains unchanged in Stop mode, the core cannot be restarted via the
HI08 interface. Do not issue a STOP command to the DSP via the HI08 unless you
provide some other mechanism to exit stop mode.
IRQA
,
IRQB
interrupt routines), and perform control or debugging
DSP56309 User’s Manual, Rev. 1
Host Programmer Model
6-21