BGW200EG/01,515 NXP Semiconductors, BGW200EG/01,515 Datasheet - Page 13

• Manufacturer Part Number: BGW200EG/01,515
• Description: IC WLAN SIP MOD 802.11B 68HVQFN
• Manufacturer: NXP Semiconductors
• Series: BGW200r

Specifications of BGW200EG/01,515

• Frequency: 2.4GHz ~ 2.5GHz
• Modulation Or Protocol: DBPSK, DQPSK, CCK
• Applications: PDA's, Portable Audio/Video, Smartphones
• Power - Output: 8dBm ~ 18dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Package / Case: 68-VQFN Exposed Pad, 68-HVQFN, 68-SQFN, 68-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Operating Temperature: -
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Other names: 568-4015-2; 935279198515; BGW200EG/01-G

NXP Semiconductors
9. SA2411 RF power amplifier
10. SA2443A IEEE 802.11b medium access controller and modem
BGW200EG_1
Product data sheet
10.1 System configuration unit
Upon entering the TX mode, the ramping-up of the RF TX signal is delayed by an internal
power ramping circuit. The ramping-up time is fixed while the delay prior to ramping-up
can be programmed by register settings. There is 15 dB of gain control with 1 dB
resolution. A gain adjustment range of 0 dB to 7 dB in 1 dB steps is provided in the TX
reconstruction filter. An additional 8 dB of gain control is provided in the upconverters via a
single 8 dB gain step.
The power stage of the transmit amplifier is a fixed gain, class AB amplifier designed to
give typically 18 dBm output power at the antenna pin for an 11 Msymbol/s CCK
modulation. The device has differential inputs and an integrated balun and harmonic filter
at the output. The integrated power detector detects the power level and transforms it into
a low-frequency voltage input for the baseband.
The 44 MHz reference clock for the SA2443A is supplied by the SA2405.
Power consumption is substantially reduced in doze mode using a low-frequency sleep
clock. The sleep clock can be derived from an internal 1 MHz oscillator, located in the
clock generation block, or supplied externally (typically 32 kHz).
The clock generation block generates all clocks required by the SA2443A from the
44 MHz, 1 MHz and 32 kHz clocks. The microcontroller and bus clock frequency can be
configured between 32 kHz and 66 MHz to allow power consumption to be optimized.
Fig 4. Block diagram of the system configuration unit
LOADSCR1
LOADSCR0
CLK44M
Rev. 01 — 18 July 2007
CLK32K
POR_N
RST_N
CONFIGURATION
GENERATION
GENERATION
REGISTERS
SYSTEM
CLOCK
RESET
firmware
reset
001aad189
IEEE 802.11b System-in-Package
clocks
watchdog reset
SPI2 reset
SDIO reset
reset
VPB
BGW200EG
© NXP B.V. 2007. All rights reserved.
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