BGW200EG/01,515 NXP Semiconductors, BGW200EG/01,515 Datasheet - Page 27

• Manufacturer Part Number: BGW200EG/01,515
• Description: IC WLAN SIP MOD 802.11B 68HVQFN
• Manufacturer: NXP Semiconductors
• Series: BGW200r

Specifications of BGW200EG/01,515

• Frequency: 2.4GHz ~ 2.5GHz
• Modulation Or Protocol: DBPSK, DQPSK, CCK
• Applications: PDA's, Portable Audio/Video, Smartphones
• Power - Output: 8dBm ~ 18dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Package / Case: 68-VQFN Exposed Pad, 68-HVQFN, 68-SQFN, 68-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Operating Temperature: -
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Other names: 568-4015-2; 935279198515; BGW200EG/01-G

NXP Semiconductors
BGW200EG_1
Product data sheet
10.14.1 SPI interface
10.14.2 Mailboxes and scratch registers
The SPI interface operates entirely in the SPI clock domain. This enables the use of a
higher SPI clock frequency than would be allowed with the usual oversampling scheme.
SPI2 clock frequencies of up to 66 MHz are allowed.
The SPI_SCK for SPI2 only needs to run when a data transfer is in progress. No
additional clock pulses are needed.
When the SA2443A is the only slave on the SPI bus the SPI_SS_N signal can be tied
permanently LOW, without any impact on power consumption.
The SPI interface supports mode 3 slave operation. The relationship between SPI_SCK,
SPI_MOSI and SPI_MISO is illustrated in
the rising edge of SPI_SCK. The SA2443A can be programmed (by firmware running on
the SA2443A microcontroller) to transition SPI_MISO on either the falling edge or rising
edge of SPI_SCK.
Care should be taken that none of the SPI interface signals are driven HIGH when V
lower than the minimum recommended operating voltage; see
The write register command and all initialization packets are always sent MSB first. The bit
order of the read register data, DMA size and DMA data packets can be programmed (by
firmware running on the SA2443A microcontroller) to allow either the LSB or the MSB in a
packet to be transferred first.
The SPI2 interface contains 8 mailboxes: 4 local mailboxes (SPI2_LOC_MB0 to
SPI2_LOC_MB3; see
SPI2_HST_MB3; see
The local mailboxes are written to by the host and read from by the SA2443A
microcontroller. A local SPI2 interrupt is generated when the host writes to one of the local
mailboxes. The enabling of generation of the interrupt is programmable.
Fig 18. SPI2 timing diagram
SPI_SS_N
SPI_MISO
SPI_MOSI
SPI_SCK
(output)
(input)
Table
Table
Rev. 01 — 18 July 2007
22).
20) and 4 host mailboxes (SPI2_HST_MB0 to
Figure
18. Data on SPI_MOSI is sampled on
IEEE 802.11b System-in-Package
Table
BGW200EG
66.
© NXP B.V. 2007. All rights reserved.
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