BGW200EG/01,515 NXP Semiconductors, BGW200EG/01,515 Datasheet - Page 34

• Manufacturer Part Number: BGW200EG/01,515
• Description: IC WLAN SIP MOD 802.11B 68HVQFN
• Manufacturer: NXP Semiconductors
• Series: BGW200r

Specifications of BGW200EG/01,515

• Frequency: 2.4GHz ~ 2.5GHz
• Modulation Or Protocol: DBPSK, DQPSK, CCK
• Applications: PDA's, Portable Audio/Video, Smartphones
• Power - Output: 8dBm ~ 18dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Package / Case: 68-VQFN Exposed Pad, 68-HVQFN, 68-SQFN, 68-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Operating Temperature: -
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Other names: 568-4015-2; 935279198515; BGW200EG/01-G

NXP Semiconductors
Table 24.
Legend: * reset value
[1]
Table 25.
Legend: * reset value
[1]
BGW200EG_1
Product data sheet
Bit
0
Bit
7
6
5
4
3
2
1
0
A host write to this bit will result in the SA2443A being reset.
This bit will be cleared by a local read.
Symbol
RST_SA2443A
Symbol
H2S1_INT_EN
H2S0_INT_EN
S2H1_INT_EN
S2H0_INT_EN
H2S1_INT_STAT
H2S0_INT_STAT
S2H1_INT_STAT
S2H0_INT_STAT
SPI2_RST_CR register - SPI2 reset control (19h)
SPI2_DMA_ISCR register - SPI2 DMA interrupt status and control (1Ah)
Access
Local
R
Access
Local
R/W
R/W
R/W
R/W
R
R
R
R
[1]
[1]
[1]
[1]
Host
R/W
Host
R
R
R
R
R
R
R
R
Rev. 01 — 18 July 2007
Value
0*
1
Value
0*
1
0*
1
0*
1
0*
1
0*
1
0*
1
0*
1
0*
1
…continued
Description
SA2443A reset control
do not reset SA2443A
reset SA2443A
Description
host-to-slave DMA channel 1 interrupt control
interrupt disabled
interrupt will be generated on transfer completion
host-to-slave DMA channel 0 interrupt control
interrupt disabled
interrupt will be generated on transfer completion
slave-to-host DMA channel 1 interrupt control
interrupt disabled
interrupt will be generated on transfer completion
slave-to-host DMA channel 0 interrupt control
interrupt disabled
interrupt will be generated on transfer completion
host-to-slave DMA channel 1 interrupt status
no interrupt pending
transfer complete interrupt pending
host-to-slave DMA channel 0 interrupt status
no interrupt pending
transfer complete interrupt pending
slave-to-host DMA channel 1 interrupt status
no interrupt pending
transfer complete interrupt pending
slave-to-host DMA channel 0 interrupt status
no interrupt pending
transfer complete interrupt pending
[1]
IEEE 802.11b System-in-Package
BGW200EG
© NXP B.V. 2007. All rights reserved.
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