BGW200EG/01,515 NXP Semiconductors, BGW200EG/01,515 Datasheet - Page 25

• Manufacturer Part Number: BGW200EG/01,515
• Description: IC WLAN SIP MOD 802.11B 68HVQFN
• Manufacturer: NXP Semiconductors
• Series: BGW200r

Specifications of BGW200EG/01,515

• Frequency: 2.4GHz ~ 2.5GHz
• Modulation Or Protocol: DBPSK, DQPSK, CCK
• Applications: PDA's, Portable Audio/Video, Smartphones
• Power - Output: 8dBm ~ 18dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Package / Case: 68-VQFN Exposed Pad, 68-HVQFN, 68-SQFN, 68-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Operating Temperature: -
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Other names: 568-4015-2; 935279198515; BGW200EG/01-G

NXP Semiconductors
BGW200EG_1
Product data sheet
10.13 Master/slave serial peripheral interface
The master/slave SPI interface (SPI1) has the following features:
The SPI1 interface block can be configured to work with most SPI master or slave devices.
Clock frequency, polarity (bit CPOL) and phase (bit CPHA) are configurable by firmware,
as is the data bit order (LSB first or MSB first).
The primary use of the interface is as an SPI master connected to a serial EEPROM or
flash memory. In this case, one of the GPIO pins (see
by firmware to generate the EEPROM slave select signal. When used in master mode pin
SPI_SS_N must be held HIGH to prevent a mode fault occurring.
The SPI clock is oversampled by a factor of 8. The maximum SPI1 clock frequency is
therefore limited to 1/8 of the bus clock.
The I/O pins for this interface are multiplexed with the I/O pins for the SPI2 block; see
Section
Fig 16. Block diagram of the master/slave SPI interface (SPI1)
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•
•
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Master or slave mode operation
SPI mode 0 and mode 3 supported in both master and slave modes
Programmable clock frequency up to 8.25 MHz
Automatic error checking: write collision, read overrun, mode fault and slave abort
10.14.
SPI_MOSI
SPI_MISO
SPI_SS_N
SPI_SCK
Rev. 01 — 18 July 2007
GENERATOR/
SHIFT REGISTER
DETECTOR
SPI CLOCK
INTERRUPT
SPI STATE
CONTROL
CONTROL
001aad201
IEEE 802.11b System-in-Package
Section
VPB
SPI1 interrupt
10.16) must be controlled
BGW200EG
© NXP B.V. 2007. All rights reserved.
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