BGW200EG/01,515 NXP Semiconductors, BGW200EG/01,515 Datasheet - Page 22

• Manufacturer Part Number: BGW200EG/01,515
• Description: IC WLAN SIP MOD 802.11B 68HVQFN
• Manufacturer: NXP Semiconductors
• Series: BGW200r

Specifications of BGW200EG/01,515

• Frequency: 2.4GHz ~ 2.5GHz
• Modulation Or Protocol: DBPSK, DQPSK, CCK
• Applications: PDA's, Portable Audio/Video, Smartphones
• Power - Output: 8dBm ~ 18dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Package / Case: 68-VQFN Exposed Pad, 68-HVQFN, 68-SQFN, 68-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Operating Temperature: -
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Other names: 568-4015-2; 935279198515; BGW200EG/01-G

NXP Semiconductors
BGW200EG_1
Product data sheet
10.10 System timers
The SA2443A contains five general-purpose timers and a WatchDog Timer (WDT).
Table 6
Table 6.
Timers 0, 1, 3 and 4 can be programmed with a start value. Operation can be either single
shot or continuous. An interrupt is generated when a timer counts down to zero.
Timer 2 is programmed with up to four interrupt compare values. An interrupt is generated
when the counter value matches one of the interrupt compare values. Operation can be
either one shot or continuous.
The watchdog timer provides a mechanism to reset the SA2443A if for some reason the
firmware becomes locked. A start value is programmed from which the counter counts
down to zero. For correct operation of the SA2443A the firmware must reset the start
value before the counter reaches zero. If the counter reaches zero the SA2443A is reset.
An interrupt compare value can be programmed, allowing a warning to be generated prior
to the full reset.
Timer name
TIMER0
TIMER1
TIMER2
TIMER3
TIMER4
WDT
Fig 13. Block diagram of system timers
provides an overview of the timer functionality.
Timer overview
Type
down count
down count
up count
down count
down count
down count
WDT interrupt
T2 interrupt 1
T2 interrupt 2
T2 interrupt 3
T2 interrupt 4
Rev. 01 — 18 July 2007
T0 interrupt
T1 interrupt
T3 interrupt
T4 interrupt
WDT reset
Count
frequency
bus clock
bus clock
1 MHz
1 MHz
1 MHz
1 MHz
WATCHDOG
TIMER0
TIMER1
TIMER2
TIMER3
TIMER4
TIMER
Interrupt conditions
on zero
on zero
when count matches any of four programmed
values
on zero
on zero
interrupt when count matches programmed
value; reset generated when count reaches zero
1 MHz
bus clock
001aad198
IEEE 802.11b System-in-Package
VPB
BGW200EG
© NXP B.V. 2007. All rights reserved.
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