IPR-FIR Altera, IPR-FIR Datasheet - Page 15

• Manufacturer Part Number: IPR-FIR
• Description: IP CORE Renewal Of IP-FIR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FIR

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Arria II GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Finite Impulse Response Compiler
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Design Flows
DSP Builder Flow
© December 2010 Altera Corporation
The FIR Compiler MegaCore
■
■
This chapter describes how you can use a FIR Compiler MegaCore function in either
of these flows. The parameterization is the same in each flow and is described in
Chapter 3, Parameter
After parameterizing and simulating a design in either of these flows, you can
compile the completed design in the Quartus II software.
Altera’s DSP Builder product shortens digital signal processing (DSP) design cycles
by helping you create the hardware representation of a DSP design in an algorithm-
friendly development environment.
DSP Builder integrates the algorithm development, simulation, and verification
capabilities of The MathWorks MATLAB
with Altera Quartus
can combine existing Simulink blocks with Altera DSP Builder blocks and MegaCore
function variation blocks to verify system level specifications and perform simulation.
In DSP Builder, a Simulink symbol for the FIR Compiler appears in the MegaCore
Functions library of the Altera DSP Builder Blockset in the Simulink library browser.
You can use the FIR Compiler in the MATLAB/Simulink environment by performing
the following steps:
1. Create a new Simulink model.
2. Select the FIR Compiler block from the MegaCore Functions library in the
3. Double-click the FIR Compiler block in your model to display IP Toolbench and
4. Click Step 2: Generate in IP Toolbench to generate your FIR Compiler MegaCore
5. Connect your FIR Compiler MegaCore function variation block to the other
DSP Builder: Use this flow if you want to create a DSP Builder model that
includes a FIR Compiler MegaCore function variation.
MegaWizard™ Plug-In Manager: Use this flow if you would like to create a FIR
Compiler MegaCore function variation that you can instantiate manually in your
design.
Simulink Library Browser, add it to your model, and give the block a unique
name.
click Step 1: Parameterize to parameterize a FIR Compiler MegaCore function
variation. For an example of how to set parameters for the FIR Compiler block,
refer to
function variation. For information about the generated files, refer to
page
blocks in your model.
2–6.
Chapter 3, Parameter
®
II software and third-party synthesis and simulation tools. You
Settings.
®
function supports the following design flows:
Settings.
®
and Simulink
®
2. Getting Started
system-level design tools
FIR Compiler User Guide
Table 2–1 on