IPR-FIR Altera, IPR-FIR Datasheet - Page 49

• Manufacturer Part Number: IPR-FIR
• Description: IP CORE Renewal Of IP-FIR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FIR

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Arria II GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Finite Impulse Response Compiler
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
FIR Compiler
Figure 4–4. Serial Filter Block Diagram
© December 2010 Altera Corporation
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Serial Structures
A serial structure trades off area for speed. The filter processes input data one bit at-a-
time per clock cycle. Therefore, serial structures require N clock cycles (where N is the
input data width) to calculate an output. In the Stratix IV, Stratix III, Stratix II, Stratix,
Cyclone III, Cyclone II, and Cyclone device families, using memory blocks for data
storage will result in a significant reduction in area.
Figure 4–4
Multibit Serial Structure
A multibit serial structure combines several small serial FIR filters in parallel to
generate the FIR result. This structure provides greater throughput than a standard
serial structure while using less area than a fully parallel structure, allowing you to
trade off device area for speed.
Figure 4–5
Figure 4–5. Multibit Serial Structure
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shows the serial filter block diagram.
shows the multibit serial structure.
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Bit Array Multiplier
Input
Data
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Serial
Serial
Serial
Filter
Filter
Filter
FIR
FIR
FIR
Accumulator
Serial
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yout
FIR Compiler
Created Glue
Logic
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Bit Array Multiplier
Filtered
Data
FIR Compiler User Guide
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