IPR-FIR Altera, IPR-FIR Datasheet - Page 7

• Manufacturer Part Number: IPR-FIR
• Description: IP CORE Renewal Of IP-FIR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FIR

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Arria II GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Finite Impulse Response Compiler
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 1: About This Compiler
General Description
General Description
© December 2010 Altera Corporation
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The Altera FIR Compiler provides a fully integrated finite impulse response (FIR)
filter development environment optimized for use with Altera FPGA devices.
You can use the IP Toolbench interface to implement a variety of filter architectures,
including fully parallel, serial, or multibit serial distributed arithmetic, and multicycle
fixed/variable filters. The FIR Compiler includes a coefficient generator.
Many digital systems use signal filtering to remove unwanted noise, to provide
spectral shaping, or to perform signal detection or analysis. Two types of filters that
provide these functions are finite impulse response (FIR) filters and infinite impulse
response (IIR) filters. Typical filter applications include signal preconditioning, band
selection, and low-pass filtering.
In contrast to IIR filters, FIR filters have a linear phase and inherent stability. This
benefit makes FIR filters attractive enough to be designed into a large number of
systems. However, for a given frequency response, FIR filters are a higher order than
IIR filters, making FIR filters more computationally expensive.
The structure of a FIR filter is a weighted, tapped delay line as shown in
Figure 1–1. Basic FIR Filter
Precision control of chip resource utilization:
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Support for run-time coefficient reloading capability and multiple coefficient sets.
Includes a built-in coefficient generator to enable efficient design space
exploration.
User-selectable output precision via rounding and saturation.
DSP Builder ready.
xin
Logic cells, M512, M4K, M-RAM, MLAB, M9K, or M144K for data storage.
M512, M4K, M9K, M20K, MLAB or logic cells for coefficient storage.
Includes a resource estimator.
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FIR Compiler User Guide
Tapped
Delay Line
Coefficient
Multipliers
Adder Tree
Figure
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