IPR-FIR Altera, IPR-FIR Datasheet - Page 66

• Manufacturer Part Number: IPR-FIR
• Description: IP CORE Renewal Of IP-FIR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FIR

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Arria II GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Finite Impulse Response Compiler
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–24
Figure 4–26. Multicycle Variable (Using Logic Cells) Coefficient Reloading Timing Diagram
Figure 4–27. Multicycle Variable (Using Memory Blocks) Coefficient Reloading Timing Diagram
FIR Compiler User Guide
reset_n
coef_ld
coef_we
coef_in
ast_sink_ready
ast_sink_data
ast_source_valid
ast_source_data
ast_sink_ready
ast_sink_data
coef_in_clk
coef_we
coef_in
ast_source_valid
ast_source_data
clk
clk
1
Multicycle variable reloading is faster than the fixed FIR (with reloading capability).
Coefficients need sequence adjustment using the same algorithm as fixed FIR filters
for all types of coefficient storage. The reloading clock is the same as the FIR filter
calculation clock; coef_we should be triggered by the coef_ld signal.
When the coefficients are stored in logic cells, a reloaded coefficient set reverts backs
to the original set after a reset operation.
Figure 4–26
the coefficients are stored in logic cells.
For multicycle variable FIR filters, when coefficients are stored in memory blocks,
coef_we should be effective two clock cycles before the first coef_in data, and
should last until the last coef_in data is transmitted. Coefficients can be
transmitted from c0 to cn by a different clock.
Figure 4–27
the coefficients are stored in memory blocks.
If you use multiple coefficient sets, you can update one set of coefficients while using
another set for calculation. The signals coef_set_in and coef_we are not clocked
in and pipelined synchronously. While you update the coefficient set, you need to set
and hold the coef_set_in signal for several cycles before coef_we is asserted and
after it is de-asserted.
shows the Multicycle variable coefficient reloading timing diagram when
shows the Multicycle variable coefficient reloading timing diagram when
0
5
Coef_we is valid one clock cycle after effective coef_ld
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coef_we is effective two clock cycles before first coef_in data
0
0
0
0
-114
-12
Input coefficients coef_in are sequence adjusted
-12
-10
Coefficients from c0 to cN
-10
© December 2010 Altera Corporation
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Chapter 4: Functional Description
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Timing Diagrams
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