IPR-FIR Altera, IPR-FIR Datasheet - Page 50

• Manufacturer Part Number: IPR-FIR
• Description: IP CORE Renewal Of IP-FIR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FIR

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Arria II GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Finite Impulse Response Compiler
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–8
Interpolation and Decimation
FIR Compiler User Guide
1
1
Figure 4–6
Figure 4–6. Fixed FIR Filters: Area Vs. Throughput
Two serial filters operating in parallel compute the result at twice the rate of a single
serial filter. Three serial filters operate at triple the speed; four operate at four times
the speed. For example, a 16-bit serial FIR filter requires 16 clock cycles to complete a
single FIR calculation. A multibit serial FIR filter with two serial structures takes only
eight clock cycles to compute the result. Using four serial structures, only four clock
cycles are required to perform the computation. Three serial structures cannot be used
for a 16-bit serial structure, however, because 16 does not divide evenly by three.
Multichannel Structures
When designing DSP systems, you may need to generate two FIR filters that have the
same coefficients. If high speed is not required, your design can share one filter, which
uses fewer resources than two individual filters. For example, a two-channel parallel
filter requires two clock cycles to calculate two outputs. The resulting hardware
would need to run at twice the data rate of an individual filter.
To minimize the number of logic elements, use a distributed serial arithmetic
architecture, multiple channels, and memory blocks for data and coefficient storage.
You can use the FIR Compiler to interpolate or decimate a signal. Interpolation
generates extra points in between the original samples; decimation removes
redundant data points. Both operations change the effective sample rate of a signal.
The outputs from interpolating and decimating filters that have the same input data
are likely to be different. This difference is because changing the delay between the
reset signal and the first non-zero input data sample may make the input sample go
down a different path of the polyphase filter. This means that the input data is
multiplied by a different set of coefficients and the filter results are different.
shows the area/speed “trade-off” of fixed FIR filters.
Throughput
Serial
Area
Multi-Bit
Serial
With Extended
Pipelining
Parallel
With Extended
Pipelining
© December 2010 Altera Corporation
Chapter 4: Functional Description
With Extended
Pipelining
FIR Compiler