IPR-FIR Altera, IPR-FIR Datasheet - Page 18

• Manufacturer Part Number: IPR-FIR
• Description: IP CORE Renewal Of IP-FIR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FIR

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Arria II GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Finite Impulse Response Compiler
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

2–4
FIR Compiler User Guide
Figure 2–3. IP Toolbench—Parameterize
2. Click Step 2: Setup Simulation in IP Toolbench to display the Set Up Simulation -
Figure 2–4. Set Up Simulation
3. Turn on Generate Simulation Model to create an IP functional model.
FIR Compiler page
1
An IP functional simulation model is a cycle-accurate VHDL or Verilog
HDL model produced by the Quartus II software.
(Figure
2–4).
© December 2010 Altera Corporation
MegaWizard Plug-In Manager Flow
Chapter 2: Getting Started