IPR-FIR Altera, IPR-FIR Datasheet - Page 63

• Manufacturer Part Number: IPR-FIR
• Description: IP CORE Renewal Of IP-FIR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FIR

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Arria II GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Finite Impulse Response Compiler
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Timing Diagrams
Figure 4–20. Single Channel, Interpolation-by-2 (Parallel, MCV Single Cycle), ast_sink_ready Control
Figure 4–21. Three Channel, Interpolation-by-2 (Parallel, MCV Single Cycle)
Decimation Filter Timing Diagrams
© December 2010 Altera Corporation
These timing diagrams also apply to an MCV single cycle filter. An interpolation-by-2
filter produces two output data for each input data it receives. As seen from the
figures, a new output is produced every cycle. This means that new input data is
required every other cycle.
This behavior can be observed easily when the flow of data is controlled by the
ast_sink_valid signal as in
Figure 4–21
with a Parallel or MCV single cycle architecture illustrating the additional start of
packet and end of packet signals.
The timing diagrams for Serial, Multibit serial, and MCV multicycle filters would be
similar to
value of N, and interpolation factor M, new input data is required every N×M clock
cycles and a new output would be produced every M clock cycles.
In a decimation-by-M filter, for every M input data, one output will be produced.
Figure 4–22 on page 4–22
by-2 filter, new input data is taken each clock cycle and new output data is produced
every other clock cycle.
Figure 4–17
shows the timing diagram for a three channel, interpolation-by-2 filter
and
shows that for a Parallel or MCV (single cycle) decimation-
Figure
Figure
4–18. For an MCV filter with a Clocks to Compute
4–19.
FIR Compiler User Guide
4–21