IPR-FIR Altera, IPR-FIR Datasheet - Page 52

• Manufacturer Part Number: IPR-FIR
• Description: IP CORE Renewal Of IP-FIR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FIR

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Arria II GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Finite Impulse Response Compiler
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–10
Figure 4–9. Interpolation Filter Structure
FIR Compiler User Guide
input
input
1
N
Because the FIR Compiler is an automated design tool, it is possible to implement a
multichannel, multiple coefficient set interpolation or decimation filter (which is
further implemented as a multichannel, multiple coefficient set structure).
The net result of these optimization techniques is a general savings in resources.
Implementation Details for Interpolation and Decimation Structures
Figure 4–9
interpolation and decimation filters.
Figure 4–9
to compute each polyphase output. The input data must be held for the number of
clocks to compute each polyphase output multiplied by the number of polyphase
units (which is the same as the interpolation factor).
Figure 4–10 on page 4–11
Each polyphase filter must be computed prior to computing the final results. Because
there are several polyphase results that must be accumulated, it is clear that the
output will update every N clocks, where N = number of polyphase filters × number
of clocks to compute each polyphase result.
The number of polyphase filters is equal to the decimation factor. The input data must
be held for the time it takes to compute a single polyphase filter.
P(N-1)
P(0)
P(2)
P(1)
LPF
and
illustrates an interpolation structure. It takes a constant number of clocks
4–14
illustrate the results when applying polyphase decomposition to
output
shows a decimation filter (with polyphase decomposition).
output
input
Control
Circuitry
N Channel
N Coefficient Set
Single Rate FIR Filter
© December 2010 Altera Corporation
Chapter 4: Functional Description
FIR Compiler
output