IPR-FIR Altera, IPR-FIR Datasheet - Page 38

• Manufacturer Part Number: IPR-FIR
• Description: IP CORE Renewal Of IP-FIR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FIR

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Arria II GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Finite Impulse Response Compiler
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–14
Table 3–6. Multibit Serial Filter Architecture (Part 2 of 2)
Table 3–7. Fully Parallel Filter Architecture
FIR Compiler User Guide
Coefficient Reload
Pipeline Level
Use Single Clock
Note to
(1) The bit width of input data should divide evenly by the number of serial units and result of division must be greater than or equal to four.
Data Storage
Coefficient Storage
Force Non-Symmetric
Structure
Coefficient Reload
Pipeline Level
Use Single Clock
Note to
(1) When input data is unsigned, the input data bit width should be greater than or equal to one. When input data is signed, the input data bit width
should be greater than or equal to two.
Parameters
Parameters
Table
Figure
3–6:
3–6:
If you want to change coefficients, turn on this option. This option is available when you choose to
store coefficients in embedded memory.
Selecting this option increases resource usage, turns off several optimization schemes, and adds
additional input ports to the filter.
Creates a higher performance filter with a resource usage increase.
Use this option when creating designs with DSP Builder. This option is only available when
Coefficients Reload is selected and M512, M4K, MLAB or M9K is specified in Coefficient Storage.
This option ties the coef_clk_in and clk signals together.
Specifies the device resources used for data storage. You can select Logic Cells or Auto. If you
select Auto, the Quartus II software may store data in logic cells or memory, depending on the
resources in the selected device, the size of the data storage, and the number of input channels.
Specifies the device resources used for coefficient storage. You can select Logic Cells, M512,
M4K, MLAB, M9K, or Auto. If you select Auto, the Quartus II software automatically selects the
most appropriate memory block size for the selected device.
The option list changes depending on which device you select. Selecting embedded memory
reduces logic cell usage and may increase the speed of the filter.
If you want to create a design that uses both symmetric and non-symmetric coefficients, turn on
this option. Non-symmetric architectures may use more resources.
This option is available when coefficients are stored in the embedded memory.
If you want to change coefficients, turn on this option. This option is available when you choose to
store coefficients in embedded memory.
Selecting this option increases resource usage, turns off several optimization schemes, and adds
additional input ports to the filter.
Creates a higher performance filter with a resource usage increase.
Use this option when creating designs with DSP Builder. This option is only available when
Coefficients Reload is selected and M512, M4K, MLAB or M9K is specified in Coefficient Storage.
This option ties the coef_clk_in and clk signals together.
(Note 1)
(Note 1)
Description
Description
© December 2010 Altera Corporation
Specify the Architecture Specification
Chapter 3: Parameter Settings