IPR-FIR Altera, IPR-FIR Datasheet - Page 45

• Manufacturer Part Number: IPR-FIR
• Description: IP CORE Renewal Of IP-FIR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FIR

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Arria II GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Finite Impulse Response Compiler
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
FIR Compiler
© December 2010 Altera Corporation
1
Symmetrical Architecture Selection
Many FIR filters have symmetrical coefficient values. The FIR Compiler examines the
coefficients and automatically determines the filter’s symmetry: even, odd, or none.
After detecting symmetry, the wizard selects an optimum algorithm to minimize the
amount of computation needed. The FIR compiler determines coefficient symmetry
after the coefficients are rounded. If symmetry is present, two data points are added
prior to the multiplication step, saving a multiplication operation (taking advantage
of filter symmetry reduces the number of multipliers by about half).
The wizard gives you the option to force non-symmetrical structures. If the
symmetry-optimized architecture is not available, this option is disabled.
Odd and even filter structures are shown in
Figure 4–1. Seven-Tap Symmetrical FIR Filter
Symmetrical Serial
Symmetrical serial filters take an additional clock cycle to perform the FIR
computation (so the filter can compute the carry). Additional logic cells are required
for the symmetrical adder resources.
Because non-symmetrical serial FIR filters do not require this resource, non-
symmetrical filters may be smaller and/or faster.
You can use the Resource Estimator in the Architecture Specification area of the
Parameterize FIR Compiler page to determine the best solution available. Refer to
Figure 3–9 on page
Data In
3–15).
Z
-1
C
0
Z
-1
Z
-1
C
1
Figure 4–1
Z
-1
Z
-1
Data Out
C
and
2
Figure
Z
-1
4–2.
FIR Compiler User Guide
Z
C
3
-1
4–3