IPR-FIR Altera, IPR-FIR Datasheet - Page 9

• Manufacturer Part Number: IPR-FIR
• Description: IP CORE Renewal Of IP-FIR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FIR

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Arria II GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Finite Impulse Response Compiler
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 1: About This Compiler
General Description
Figure 1–3. Typical Modulator System
© December 2010 Altera Corporation
Input
Data
Reed Solomon
Encoder
FEC
Outer Encoding Layer
Figure 1–3
DSP processors have a limited number of multiply accumulators (MACs), and require
many clock cycles to compute each output value (the number of cycles is directly
related to the order of the filter).
A dedicated hardware solution can achieve one output per clock cycle. A fully
parallel, pipelined FIR filter implemented in an FPGA can operate at very high data
rates, making FPGAs ideal for high-speed filtering applications.
Table 1–4
a 120-tap FIR filter with a 12-bit data input bus.
Table 1–4. FIR Filter Implementation Comparison
The FIR Compiler speeds the design cycle by:
■
■
■
■
DSP processor
FPGA
Note to
(1) If you use the FIR Compiler to create a filter, you can also implement a variable filter in a FPGA that uses from 1
Generating the coefficients needed to design custom FIR filters.
Generating bit-accurate and clock-cycle-accurate FIR filter models (also known as
bit-true models) in the Verilog HDL and VHDL languages and in the MATLAB
environment.
Automatically generating the code required for the Quartus II software to
synthesize high-speed, area-efficient FIR filters of various architectures.
Generating a VHDL testbench for all architectures.
Convolutional
Interleaver
to 120 MACs, and 120 to 1 clock cycles.
Table
compares resource usage and performance for different implementations of
shows a typical DSP system that uses Altera MegaCore functions.
Device
1–4:
Convolutional
Encoder
(Viterbi)
Inner Coding Layer
Constellation
1 MAC
1 serial filter
1 parallel filter
Mapper
Implementation
Q
I
FIR Compiler
FIR Compiler
(Note 1)
N
N
LPF
LPF
120
12
1
Compiler
NCO
Compute Result
Clock Cycles to
FIR Compiler User Guide
DAC
Output
Data
1–5