IPR-FIR Altera, IPR-FIR Datasheet - Page 8

• Manufacturer Part Number: IPR-FIR
• Description: IP CORE Renewal Of IP-FIR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FIR

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Arria II GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Finite Impulse Response Compiler
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

1–4
Figure 1–2. Design Cycle Comparison
FIR Compiler User Guide
Traditional Flow
FIR Filter
Design
6 Weeks
The filter design process involves identifying coefficients that match the frequency
response specified for the system. These coefficients determine the response of the
filter. You can change which signal frequencies pass through the filter by changing the
coefficient values or adding more coefficients.
Traditionally, designers have been forced to make a trade-off between the flexibility of
digital signal processors and the performance of ASICs and application-specific
standard product (ASSPs) digital signal processing (DSP) solutions. The Altera DSP
solution reduces the need for this trade-off by providing exceptional performance
combined with the flexibility of FPGAs.
Figure 1–2
traditional implementation.
Design Structural or Synthesizable
Define & Design Architectural
Synthesize & Place & Route
Characteristics of FIR Filter
Calculate Filter Coefficients
Determine Hardware Filter
Area/Speed Tradeoff
Determine Behavioral
Architecture
Simulate
compares the design cycle using a FIR Compiler MegaCore function with a
(MATLAB)
FIR Filter
Blocks
FIR Compiler Flow
FIR Filter Design
1 Day
to FIR Compiler Megafunction
(FIR Compiler Assists in Area/
Define & Design Architectural
Synthesize & Place & Route
Specify Filter Characteristics
Speed Tradeoff)
Simulate
Blocks
© December 2010 Altera Corporation
Chapter 1: About This Compiler
General Description