IPR-FIR Altera, IPR-FIR Datasheet - Page 22

• Manufacturer Part Number: IPR-FIR
• Description: IP CORE Renewal Of IP-FIR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FIR

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Arria II GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Finite Impulse Response Compiler
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

2–8
Simulate the Design
FIR Compiler User Guide
f
Figure 2–7. Port Lists in the Generation Report
2. After you review the generation report, click Exit to close IP Toolbench. Then click
To simulate your design in Verilog HDL or VHDL, use the IP functional simulation
models generated by IP Toolbench.
The IP functional simulation model is the .vo or .vho file (located in your design
directory) generated as specified in Step
For more information about IP functional simulation models, refer to the
Altera Designs
Simulating in ModelSim
A Tcl script (<variation name>_msim.tcl) is also generated which can be used to load
the VHDL testbench into the ModelSim simulator.
This script uses the file <variation name>_input.txt to provide input data to the FIR
filter. The output from the simulation is stored in a file <variation name>_output.txt.
The generation report also lists the ports defined in the MegaCore function
variation file
external ports for your MegaCore function variation, refer to
page
Yes on the Quartus II IP Files prompt to add the .qip file describing your custom
MegaCore function variation to the current Quartus II project.
4–16.
chapter in volume 3 of the Quartus II Handbook.
(Figure
2–7). For a full description of the signals supported on
1
on
page
2–3.
© December 2010 Altera Corporation
MegaWizard Plug-In Manager Flow
Table 4–3 on
Chapter 2: Getting Started
Simulating