ADUC7039BCP6Z-RL Analog Devices Inc, ADUC7039BCP6Z-RL Datasheet - Page 18

• Manufacturer Part Number: ADUC7039BCP6Z-RL
• Description: Flash 64k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7039BCP6Z-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption

ADuC7039
Command Sequence for Executing a Mass Erase
Given the significance of the mass erase command, a specific code sequence must be executed to initiate this operation.
1.
2.
3.
4.
5.
This sequence is illustrated in the following example:
Int a = FEESTA;
FEEMOD = 0x08
FEEADR = 0xFFC3
FEEDAT = 0x3CFF
FEECON = 0x06;
while (FEESTA & 0x04){}
FEESTA Register
Name:
Address:
Default Value:
Access:
Function:
Table 11. FEESTA MMR Bit Designation
Bit
15 to 4
3
2
1
0
Ensure FEESTA is cleared.
Set Bit 3 in FEEMOD.
Write 0xFFC3 in FEEADR.
Write 0x3CFF in FEEDAT.
Run the mass erase command (0x06) in FEECON.
FEESTA
0xFFFF0E00
0xXXX0
Read only
This 16-bit, read-only register can be read by user code and reflects the current status of the Flash/EE memory controller.
Description
Reserved.
Flash/EE interrupt status bit.
This bit is set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt
enable bit in the FEEMOD register is set.
This bit is cleared automatically when the FEESTA register is read by user code.
Flash/EE controller busy.
This bit is set automatically when the Flash/EE controller is busy.
This bit is cleared automatically when the controller is not busy.
Command fail.
This bit is set automatically when a command written to FEECON completes unsuccessfully.
This bit is cleared automatically when the FEESTA register is read by user code.
Command successful.
This bit is set automatically by MCU when a command is completed successfully.
This bit is cleared automatically when the FEESTA register is read by user code.
// Ensure FEESTA is cleared
//Mass erase command
//Wait for command to finish
Rev. B | Page 18 of 92