ADUC7039BCP6Z-RL Analog Devices Inc, ADUC7039BCP6Z-RL Datasheet - Page 20

• Manufacturer Part Number: ADUC7039BCP6Z-RL
• Description: Flash 64k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7039BCP6Z-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption

ADuC7039
FLASH/EE MEMORY SIGNATURE
The entire 62 kB or the part of Flash/EE memory available to
the user can be signed using the FEESIG register and signature
command.
This feature automatically reads the code in that section of the
memory specified by the FEEADR and FEEDAT MMRS:
•
•
Example of User Code Signature
Int a = FEESTA;
FEEADR = 0x0000;
FEEDAT = 0x0600;
FEECON = 0x0B;
while (FEESTA & 0x04){}
User code can compare the content of FEESIG with the content of Address 0x805FC.
Polynomial
A software routine is provided by
FEEADR contains an address situated in the first half page
of the section to be signed.
FEEDAT contains an address situated in the first half page
above the last page of the section to be signed. See Figure 7
in this example, Page 0 and Page 1 are signed.
0x80400
0x80200
0x80000
Figure 7. Signature Command Indexing
PAGE 1
PAGE 0
Analog Devices,
FEEDAT = 0x04XX
FEEADR = 0x00XX
// Ensure FEESTA is cleared
// Start page address
// Stop (page + 1) address
// Signs Page 0 to Page 2 excluding
// Address 0x805FC
// Wait for command to finish
Inc., to calculate the unique 24-bit signature.
Rev. B | Page 20 of 92
•
•
•
This feature is also used by the on-chip kernel at power-up to
check the validity of Page 0 before jumping to user code. Store
the signature of Page 0 at Address 0x801FC when programming
the device. See the ADUC7039 Kernel section for more details.
Flash/EE Memory Signature Registers
Name:
Address:
Default Value:
Access:
Function:
If the 8 MSB of FEEADR and FEEDAT are identical, that
is, the MMRS point to the same page, nothing is signed.
The last two 16-bit locations are not included in the
signature; they are reserved for the user-programmed
signature.
It is possible to sign half pages, by specifying a half page
address in FEEADR and FEEDAT. For example, to sign
the second half of Page 0 and the first half of Page 1,
FEEADR = 0x0100 and FEEDAT = 0x0300.
FEESIG
0xFFFF0E18
Updated by kernel
Read only
This MMR contains a 24-bit signature of the
Flash/EE memory.