ADUC7039BCP6Z-RL Analog Devices Inc, ADUC7039BCP6Z-RL Datasheet - Page 41

• Manufacturer Part Number: ADUC7039BCP6Z-RL
• Description: Flash 64k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7039BCP6Z-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption

Current Channel ADC Result Counter Limit Register
Name:
Address:
Default Value:
Access:
Function:
Current Channel ADC Result Count Register
Name:
Address:
Default Value:
Access:
Function:
ADC0RCL
0xFFFF0548
0x0001
Read/write
This 16-bit MMR sets the number of conver-
sions required before an ADC interrupt is
generated. By default, this register is set to
0x01. The ADC counter function must be
enabled via the ADC result counter enable
bit in the ADCCFG MMR.
ADC0RCV
0xFFFF054C
0x0000
Read only
This 16-bit, read-only MMR holds the current
number of I-ADC conversion results. It is used
in conjunction with ADC0RCL to mask I-ADC
interrupts, generating a lower interrupt rate.
When ADC0RCV = ADC0RCL, the value in
ADC0RCV resets to 0 and recommences
counting. It can also be used in conjunction
with the accumulator (ADC0ACC) to allow an
average current calculation to be undertaken.
The result counter is enabled via ADCCFG[0].
This MMR is also reset to 0 when the I-ADC is
reconfigured, that is, when the ADC0CON or
ADCMDE are written.
Rev. B | Page 41 of 92
Current Channel ADC Threshold Register
Name:
Address:
Default Value:
Access:
Function:
Current Channel ADC Accumulator Register
Name:
Address:
Default Value:
Access:
Function:
ADC0TH
0xFFFF0550
0x0000
Read/write
This 16-bit MMR sets the threshold against
which the absolute value of the I-ADC
conversion result is compared. In unipolar
mode, ADC0TH[15:0] are compared and in
twos complement mode, ADC0TH[14:0] are
compared.
ADC0ACC
0xFFFF055C
0x00000000
Read only
This 32-bit MMR holds the current
accumulator value. The I-ADC ready bit
in the ADCSTA MMR should be used to
determine when it is safe to read this MMR.
The MMR value is reset to 0 by disabling
the accumulator in the ADCCFG MMR or
reconfiguring the current channel ADC.
ADuC7039