ADUC7039BCP6Z-RL Analog Devices Inc, ADUC7039BCP6Z-RL Datasheet - Page 49

• Manufacturer Part Number: ADUC7039BCP6Z-RL
• Description: Flash 64k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7039BCP6Z-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption

The operating mode and clocking mode are controlled using
two MMRs, PLLCON and POWCON, and the status of the
PLL, PLL lock and PLL interrupt, is indicated by PLLSTA.
It is recommended that before powering down the ADuC7039,
switch the clock source for the PLL to the low power oscillator
to reduce wake-up time. The low power oscillator is always
active.
When the ADuC7039 wakes up from power-down, the MCU
core begins executing code as soon as the PLL begins oscillat-
ing. This occurs before the PLL has locked to a frequency of
20.48 MHz. To ensure the Flash/EE memory controller is execut-
ing with a valid clock, the controller is driven with a PLL output
divide-by-eight clock source while the PLL is locking. When
the PLL locks, the PLL output is switched from the PLL output
divide-by-eight to the locked PLL output.
An example of writing to both MMRs is as follows:
For programming the POWCON MMR:
; Void PowerDown (void)
PowerDown PROC
ENDP
For programming the PLLCON MMR:
PLLKEY0
PLLCON
PLLKEY1
iA1*iA2
change
LDR
LDR
LDR
MOVS
STR
MOVS
STR
MOVS
STR
UMLAL
BX
r2, = 0x98765432
r3, = 0x12345678
r0, = 0xffff0400
r1,#0x1
r1,[r0,#4]
r1,#0x01
r1,[r0,#8]
r1,#0xf4
r1,[r0,#0xc]
r1,r3,r2,r0
lr
=
=
=
0xAA
0x1
0x55
//PLLCON key
//Switch to precision oscillator.
//PLLCON key
//PSEUDOCODE-dummy cycle to prevent Flash/EE access during clock
; Load random number for multiplication
;Base address
;POWKEY0 = 1
;Set POWKEY0
;Set POWCON value to recommended value of 0x01 to ensure a
;Set POWKEY1
;longest possible assembly multiplication instruction
;Flush ARM7 pipeline
10 MHz core clock
Rev. B | Page 49 of 92
If user code requires an accurate PLL output, user code must
poll the lock bit (PLLSTA[1]) after wake-up before resuming
normal code execution.
The PLL is locked within 2 ms after waking up.
PLLCON is a protected MMR with two 32-bit keys: PLLKEY0
(prewrite key) and PLLKEY1 (postwrite key).
PLLKEY0 = 0x000000AA
PLLKEY1 = 0x00000055
POWCON is a protected MMR with two 32-bit keys:
POWKEY0 (prewrite key) and POWKEY1 (postwrite key).
POWKEY0 = 0x00000001
POWKEY1 = 0x000000F4
ADuC7039