ADUC7039BCP6Z-RL Analog Devices Inc, ADUC7039BCP6Z-RL Datasheet - Page 37

• Manufacturer Part Number: ADUC7039BCP6Z-RL
• Description: Flash 64k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7039BCP6Z-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption

ADC Filter Register
Name:
Address:
Default Value:
Access:
Function:
Note:
Table 31. ADCFLT MMR Bit Designations
1
Bit
15
14
13 to 8
7
6 to 0
Due to limitations on the digital filter internal data path, there are some limitations on the combinations of the sinc3 decimation factor (SF) and averaging factor (AF)
that can be used to generate a required ADC output rate. This restriction limits the minimum ADC update to 10 Hz.
ADCFLT
0xFFFF0518
0x0007
Read/write
The ADC filter MMR is a 16-bit register that controls the speed and resolution of the on-chip ADCs.
If ADCFLT is modified, the current and voltage/temperature ADCs are reset. It is recommended that all bits of this
MMR are written in a single write operation.
Description
Chop enable.
This bit is set by the user to enable system chopping of all active ADCs. When this bit is set, the ADC has very low offset
errors and drift, but the ADC output rate is reduced by a factor of three if AF = 0 (see sinc3 decimation factor, Bits[6:0] in
this table). If AF > 0, then the ADC output update rate is the same with chop on or off. When chop is enabled, the
settling time is two output periods.
Running average.
This bit is set by the user to enable a running-average-by-two function reducing ADC noise. This function is automatically
enabled when chopping is active. It is an optional feature when chopping is inactive, and if enabled (when chopping
is inactive) does not reduce the ADC output rate but does increase the settling time by one conversion period.
This bit is cleared by the user to disable the running average function.
Averaging factor (AF).
The values written to these bits are used to implement a programmable first-order sinc3 postfilter. The averaging factor
can further reduce ADC noise at the expense of the output rate as described in Bits[6:0] sinc3 decimation factor in this
table.
Sinc3 modify.
This bit is set by the user to modify the standard sinc3 frequency response to increase the filter stop-band rejection by
approximately 5 dB. This is achieved by inserting a second notch (NOTCH2) at
where f
Sinc3 decimation factor (SF)
The value (SF) written in these bits controls the oversampling (decimation factor) of the sinc3 filter. The output rate
from the sinc3 filter is given by
when the chop bit (Bit 15, chop enable) = 0 and the averaging factor (AF) = 0. This is valid for all SF values ≤ 125.
For SF = 126, f
For SF = 127, f
For information on calculating the f
f
f
NOTCH2
ADC
NOTCH
= (512,000/([SF + 1] × 64)) Hz
= 1.333 × f
is the location of the first notch in the response.
ADC
ADC
is forced to 60 Hz.
is forced to 50 Hz.
NOTCH
1
.
ADC
for SF (other than 126 and 127) and AF values, refer to Table 32.
Rev. B | Page 37 of 92
ADuC7039