ADUC7039BCP6Z-RL Analog Devices Inc, ADUC7039BCP6Z-RL Datasheet - Page 9

• Manufacturer Part Number: ADUC7039BCP6Z-RL
• Description: Flash 64k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7039BCP6Z-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11, 14, 15
12
13
16, 17
18, 19
20
Mnemonic
RESET
TDO
TCK
TMS
TDI
NTRST
RTCK
NC
GND_SW
VTEMP
AGND
IIN+
IIN−
REG_AVDD
REG_DVDD
DGND
Type
I
O
I
I
I
I
O
I
I
S
I
I
S
S
S
1
Description
Reset Input Pin. Active low. This pin has an internal, weak, pull-up resistor to REG_DVDD. When not in
use, this pin can be left unconnected. For added security and robustness, it is recommended that this
pin be strapped via a resistor to REG_DVDD.
JTAG Test Data Output. This data output pin is one of the standard 6-pin JTAG debug ports on the
part. TDO is an output pin only. At power-on, this output is disabled and pulled high via an internal,
weak, pull-up resistor. This pin can be left unconnected when not in use.
JTAG Test Clock. This clock input pin is one of the standard 6-pin JTAG debug ports on the part. TCK
is an input pin only and has an internal, weak, pull-up resistor. This pin can be left unconnected when
not in use.
JTAG Test Mode Select. This mode select input pin is one of the standard 6-pin JTAG debug ports on
the part. TMS is an input pin only and has an internal, weak, pull-up resistor. This pin can be left
unconnected when not in use.
JTAG Test Data Input. This data input pin is one of the standard 6-pin JTAG debug ports on the part.
TDI is an input pin only and has an internal, weak, pull-up resistor. This pin can be left unconnected
when not in use.
JTAG Test Reset. This reset input pin is one of the standard 6-pin JTAG debug ports on the part.
NTRST is an input pin only and has an internal, weak, pull-down resistor. This pin can be left uncon-
nected when not in use. NTRST is also monitored by the on-chip kernel to enable LIN boot load mode.
JTAG Return Test Clock. This output pin is used to adjust the JTAG clock speed to the highest possible
rate of the ADuC7039.
No Connect. This pin is internally connected; therefore, do not externally connect this pin.
Switch to Internal Analog Ground Reference. This pin is the negative input for the external temperature
channel and external reference. If this input is not used, connect it directly to the AGND system ground.
External Pin for NTC/PTC Temperature Measurement.
Ground Reference for On-Chip Precision Analog Circuits.
Positive Differential Input for Current Channel.
Negative Differential Input for Current Channel.
Nominal 2.6 V analog Output from On-Chip Regulator. Pin 16 and Pin 17 must be connected together
to a capacitor to ground.
Nominal 2.6 V digital Output from On-Chip Regulator. Pin 18 and Pin 19 must be connected together
to capacitors to ground.
Ground Reference for On-Chip Digital Circuits.
RESET
NTRST
NOTES:
1. FOR DETAILS ON NC PINS, SEE THE PIN FUNCTION
2. EPAD IS INTERNALLY CONNECTED TO DGND.
RTCK
TDO
TCK
TMS
DESCRIPTIONS TABLE.
TDI
NC
1
2
3
4
5
6
7
8
Figure 3. Pin Configuration
ADuC7039
(Not to Scale)
Rev. B | Page 9 of 92
TOP VIEW
24
23
22
21
20
19
18
17
GPIO_3/MOSI
GPIO_2/MISO
GPIO_1/SCLK
GPIO_0/SS
DGND
REG_DVDD
REG_DVDD
REG_AVDD
ADuC7039