ADUC7039BCP6Z-RL Analog Devices Inc, ADUC7039BCP6Z-RL Datasheet - Page 74

• Manufacturer Part Number: ADUC7039BCP6Z-RL
• Description: Flash 64k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7039BCP6Z-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption

ADuC7039
SPI Status Register
Name:
Address:
Default Value:
Access:
Function:
Table 54. SPISTA MMR Bit Designations
Bit
15 to 12
11
10 to 8
7
6
5
4
3 to 1
0
Description
Reserved bits.
SPI Rx FIFO excess bytes present.
This bit is set when there are more bytes in the Rx FIFO than indicated in the SPIRXMDE bits in SPICON.
This bit is cleared when the number of bytes in the FIFO is equal or less than the number in SPIRXMDE.
SPI Rx FIFO status bits.
[000] = Rx FIFO is empty.
[001] = 1 valid byte in the FIFO.
[010] = 2 valid byte in the FIFO.
[011] = 3 valid byte in the FIFO.
[100] = 4 valid byte in the FIFO.
SPI Rx FIFO overflow status bit.
This bit is set when the Rx FIFO was already full when new data was loaded to the FIFO. This bit generates an interrupt except
when SPICON[12] is set.
This bit is cleared when the SPISTA register is read.
SPI Rx IRQ status bit.
This bit is set when a receive interrupt occurs. This bit is set when SPICON[6] is cleared and the required number of bytes have
been received.
This bit is cleared when the SPISTA register is read.
SPI Tx IRQ status bit.
This bit is set when a transmit interrupt occurs. This bit is set when SPICON[6] is set and the required number of bytes have been
transmitted.
This bit is cleared when the SPISTA register is read.
SPI Tx FIFO underflow.
This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt except when
SPICON[13] is set.
This bit is cleared when the SPISTA register is read.
SPI Tx FIFO status bits.
000 = Tx FIFO is empty.
001 = 1 valid byte in the FIFO.
010 = 2 valid byte in the FIFO.
011 = 3 valid byte in the FIFO.
100 = 4 valid byte in the FIFO.
SPI interrupt status bit.
This bit is set to 1 when an SPI-based interrupt occurs.
This bit is cleared after reading SPISTA.
SPISTA
0xFFFF0A00
0x0000
Read only
This 16-bit MMR contains the status of the SPI interface in both master and slave modes.
Rev. B | Page 74 of 92