ADUC7039BCP6Z-RL Analog Devices Inc, ADUC7039BCP6Z-RL Datasheet - Page 48
![no-image](/images/manufacturer_photos/0/0/57/analog_devices_inc_sml.jpg)
ADUC7039BCP6Z-RL
Manufacturer Part Number
ADUC7039BCP6Z-RL
Description
Flash 64k ARM7 Dual 16-Bit ADC LIN I.C.
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.EVAL-ADUC7039QSPZ.pdf
(92 pages)
Specifications of ADUC7039BCP6Z-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI
Peripherals
POR, Temp Sensor, WDT
Number Of I /o
6
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 115°C
Package / Case
32-LFCSP
Lead Free Status / RoHS Status
Lead free by exemption / RoHS compliant by exemption
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free by exemption / RoHS compliant by exemption
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADUC7039BCP6Z-RL
Manufacturer:
NS/国半
Quantity:
20 000
ADuC7039
SYSTEM CLOCKS
The ADuC7039 integrates a flexible clocking system that can
be clocked from one of two integrated on-chip oscillators: a
precision oscillator or a low power oscillator.
Each of the internal oscillators is divided by four to generate a
clock frequency of 32 kHz. The PLL locks onto a multiple (640)
of 32 kHz, supplied by either of the internal oscillators, to
provide a stable 20.48 MHz clock for the system. By default,
the PLL is driven by the low power oscillator.
The core operates at a fixed frequency of 10.24 MHz, by default.
OSCILLATOR
PRECISION
CLOCK
CORE
1
8
PLL LOCK
MCU
128kHz
DIV 4
1
2
32kHz
CONTROLLER
PLL OUTPUT
Figure 20. ADuC7039 System Clock Generation
20.48MHz
PLLCON
FLASH
PLL
OSCILLATOR
LOW POWER
32kHz
Rev. B | Page 48 of 92
CLOCK
ADC
DIVIDER
CLOCK
128kHz
ADCMDE
DIV 4
ADC
The ADC is driven by the output of the PLL, divided to give
an ADC clock source of 512 kHz. In low power mode, the ADC
clock source is switched from the standard 512 kHz to the low
power 128 kHz oscillator.
Note that the low power oscillator drives both the watchdog
and core wake-up timers through a divide-by-four circuit. A
detailed block diagram of the ADuC7039 clocking system is
shown in Figure 20.
The two integrated oscillators can be calibrated as described in
the Oscillators Calibration section.
LOW POWER
OSCILLATOR
LOW POWER
OSCILLATOR
LOW POWER
OSCILLATOR
OSCILLATOR
LOW POWER
OSCILLATOR
PRECISION
OUTPUT
CLOCK
CLOCK
CLOCK
CLOCK
CORE
CORE
CORE
CORE
PLL
HIGH ACCURACY
CALIBRATION
CALIBRATION
LOW POWER
WATCHDOG
INTERFACE
COUNTER
COUNTER
WAKE-UP
TIMER0
TIMER1
TIMER2
LIN
SPI