ADUC7039BCP6Z-RL Analog Devices Inc, ADUC7039BCP6Z-RL Datasheet - Page 29
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ADUC7039BCP6Z-RL
Manufacturer Part Number
ADUC7039BCP6Z-RL
Description
Flash 64k ARM7 Dual 16-Bit ADC LIN I.C.
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.EVAL-ADUC7039QSPZ.pdf
(92 pages)
Specifications of ADUC7039BCP6Z-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI
Peripherals
POR, Temp Sensor, WDT
Number Of I /o
6
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 115°C
Package / Case
32-LFCSP
Lead Free Status / RoHS Status
Lead free by exemption / RoHS compliant by exemption
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free by exemption / RoHS compliant by exemption
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADUC7039BCP6Z-RL
Manufacturer:
NS/国半
Quantity:
20 000
16-BIT, SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTERS
The ADuC7039 incorporates two independent sigma-delta
(Σ-Δ) analog-to-digital converters (ADCs) namely, the current
channel ADC (I-ADC), and the voltage/temperature channel
ADC (V/T-ADC). These precision measurement channels
integrate attenuator, on-chip buffering, a programmable gain
amplifier, 16-bit, Σ-Δ modulators, and digital filtering for
precise measurement of current, voltage, and temperature
variables in 12 V automotive battery systems.
Current Channel ADC (I-ADC)
The I-ADC converts battery current sensed through an external
100 μΩ shunt resistor. On-chip programmable gain means that
the I-ADC can be configured to accommodate battery current
levels from up to ±1500 A.
As shown in Figure 11, the I-ADC employs a Σ-Δ conversion
technique to realize 16 bits of no missing codes performance.
Rev. B | Page 29 of 92
The Σ-Δ modulator converts the sampled input signal into a
digital pulse train whose duty cycle contains the digital infor-
mation. A modified sinc3, programmable, low-pass filter is then
employed to decimate the modulator output data stream to give
a valid 16-bit data conversion result at programmable output
rates from 10 Hz to 1 kHz in normal and low power mode.
The I-ADC also incorporates a counter, comparator, and
accumulator logic. This allows the I-ADC result to generate an
interrupt after a predefined number of conversions have elapsed
or if the I-ADC result exceeds a programmable threshold value.
Once enabled, a 32-bit accumulator automatically sums the
16-bit I-ADC results.
The time to a first valid (fully settled) result on the current
channel is three ADC conversion cycles with chop mode turned
off and two ADC conversion cycles with chop mode turned on.
An interrupt can be generated even on unsettled ADC samples
by enabling the ADC continuous interrupt option.
ADuC7039