ADUC7039BCP6Z-RL Analog Devices Inc, ADUC7039BCP6Z-RL Datasheet - Page 19
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ADUC7039BCP6Z-RL
Manufacturer Part Number
ADUC7039BCP6Z-RL
Description
Flash 64k ARM7 Dual 16-Bit ADC LIN I.C.
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.EVAL-ADUC7039QSPZ.pdf
(92 pages)
Specifications of ADUC7039BCP6Z-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI
Peripherals
POR, Temp Sensor, WDT
Number Of I /o
6
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 115°C
Package / Case
32-LFCSP
Lead Free Status / RoHS Status
Lead free by exemption / RoHS compliant by exemption
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free by exemption / RoHS compliant by exemption
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADUC7039BCP6Z-RL
Manufacturer:
NS/国半
Quantity:
20 000
FEEMOD Register
Name:
Address:
Default Value:
Access:
Function:
Table 12. FEEMOD MMR Bit Designation
Bit
15 to 7
6 to 5
4
3
2
1
0
FEEADR Registers
Name:
Address:
Default Value:
Access:
Function:
FEEDAT Registers
Name:
Address:
Default Value:
Access:
Function:
Description
Not used. These bits are reserved for future functionality and should be written as 0 by user code.
Flash/EE security lock bits. These bits must be written as [6:5] = 1, 0 to complete the Flash/EE security protect sequence.
Flash/EE controller command complete interrupt enable.
This bit is set by user code to enable the Flash/EE controller to generate an interrupt upon completion of a Flash/EE command.
This bit is cleared by user code to disable the generation of a Flash/EE interrupt upon completion of a Flash/EE command.
Flash/EE erase/write enable.
This bit is set by user code to enable the Flash/EE erase and write access via FEECON.
This bit is cleared by user code to disable the Flash/EE erase and write access via FEECON.
Reserved.
Flash/EE controller abort enable.
This bit is set by user code to enable the Flash/EE controller abort functionality.
This bit is cleared by user code to disable the Flash/EE controller abort functionality.
Reserved.
FEEMOD
0xFFFF0E04
0x0000
Read/write
This register is written by user code to configure the mode of operation of the Flash/EE memory controller.
FEEADR
0xFFFF0E10
Updated by kernel
Read/write
This 16-bit register dictates the address upon which any Flash/EE command executed via FEECON acts.
FEEDAT
0xFFFF0E0C
0x0000
Read/write
This 16-bit register contains the data either read from, or to be written to, the Flash/EE memory.
Rev. B | Page 19 of 92
ADuC7039