ADUC7039BCP6Z-RL Analog Devices Inc, ADUC7039BCP6Z-RL Datasheet - Page 67
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ADUC7039BCP6Z-RL
Manufacturer Part Number
ADUC7039BCP6Z-RL
Description
Flash 64k ARM7 Dual 16-Bit ADC LIN I.C.
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.EVAL-ADUC7039QSPZ.pdf
(92 pages)
Specifications of ADUC7039BCP6Z-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI
Peripherals
POR, Temp Sensor, WDT
Number Of I /o
6
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 115°C
Package / Case
32-LFCSP
Lead Free Status / RoHS Status
Lead free by exemption / RoHS compliant by exemption
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free by exemption / RoHS compliant by exemption
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADUC7039BCP6Z-RL
Manufacturer:
NS/国半
Quantity:
20 000
Table 48. T2CON MMR Bit Designations
Bit
15 to 9
8
7
6
5
4
3 to 2
1
0
Description
Reserved. These bits are reserved and should be written as 0 by user code.
Count up/count down enable.
This bit is set by user code to configure Timer2 to count up.
This bit is cleared by user code to configure Timer2 to count down.
Timer2 enable.
This bit is set by user code to enable Timer2.
This bit is cleared by user code to disable Timer2.
Timer2 operating mode.
This bit is set by user code to configure Timer2 to operate in periodic mode.
This bit is cleared by user to configure Timer2 to operate in free running mode.
Watchdog timer mode enable.
This bit is set by user code to enable watchdog mode.
This bit is cleared by user code to disable watchdog mode.
Reserved. This bit is reserved and should be written as 0 by user code.
Timer2 clock prescaler.
00 = source clock/1 (default).
01 = source clock/16.
10 = source clock/256.
11 = reserved.
Watchdog timer IRQ enable.
This bit is set by user code to produce an IRQ instead of a reset when the watchdog reaches 0.
This bit is cleared by user code to disable the IRQ option.
PD_OFF.
This bit is set by the user code to stop Timer2 when the peripherals are powered down using Bit 4 in the POWCON MMR.
This bit is cleared by the user code to enable Timer2 when the peripherals are powered down using Bit 4 in the
POWCON MMR.
OSCILLATOR
LOW POWER
PRESCALER
1, 16, 256
Figure 27. Timer2 Block Diagram
Rev. B | Page 67 of 92
UP/DOWN COUNTER
16-BIT LOAD
TIMER2
VALUE
16-BIT
WATCHDOG RESET
TIMER2 IRQ
ADuC7039